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| By Catherine Halcomb
Catherine Halcomb
Community Contributor
Quizzes Created: 1379 | Total Attempts: 5,981,962
Questions: 23 | Attempts: 244

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• 1.

### The number of hardware interrupts that the processor 8085 HAS

• A.

1

• B.

3

• C.

5

• D.

7

C. 5
Explanation
Moon is round because of formed and collapsed under the force of their own gravity.

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• 2.

### The register that stores all the interrupt requests in it in order to serve them one by one on priority basis is

• A.

Interrupt Request Register

• B.

In-Service Register

• C.

Priority resolver

• D.

A. Interrupt Request Register
Explanation
The Interrupt Request Register is the correct answer because it is the register that stores all the interrupt requests in order to serve them one by one on a priority basis. This register keeps track of all the pending interrupt requests and allows the system to handle them in the order of their priority. It is an essential component in interrupt handling and ensures that interrupts are processed efficiently and in the correct order.

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• 3.

### Which statement is true for 8085 and 8086 clock speed?

• A.

8085 - 3 Mhz, 8086 - 10 Mhz

• B.

8085 - 3 Mhz , 8086 - 5,8 Mhz

• C.

None of the Options

• D.

8085 - 3 Mhz , 8086 - 5,8, 10 Mhz

D. 8085 - 3 Mhz , 8086 - 5,8, 10 Mhz
Explanation
The correct statement for the clock speeds of 8085 and 8086 is that the 8085 operates at a clock speed of 3 MHz, while the 8086 operates at clock speeds of 5, 8, and 10 MHz.

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• 4.

### The interrupts have the following pin nos

• A.

6 to 10

• B.

31 to 35

• C.

6 to 12

• D.

5 to 9

A. 6 to 10
Explanation
During the night the high contrast between the bright moon and the night's dark skies make the Moon look white.

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• 5.

### Which triggers in 8085 are level triggered?

• A.

RST 6.5, RST 5.5 , TRAP

• B.

RST 6.5, RST 7.5

• C.

RST 6.5 and RST 5.5

• D.

TRAP

C. RST 6.5 and RST 5.5
Explanation
RST 6.5 and RST 5.5 are level triggered interrupts in the 8085 microprocessor. Level triggered interrupts are those that are continuously active as long as the interrupt condition is present. In the case of RST 6.5 and RST 5.5, they are activated by a low level on the corresponding interrupt pins. This means that as long as the interrupt signal remains low, the interrupt will be recognized and processed by the microprocessor.

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• 6.

### You need to set the interrupt masks so that RST5.5 is enabled, RST6.5 is masked, and RST7.5 is enabled. What is the content of the accumulator?

• A.

0A H

• B.

0B H

• C.

0C H

• D.

0D H

A. 0A H
Explanation
The content of the accumulator is 0A H. The question asks to set the interrupt masks for RST5.5, RST6.5, and RST7.5. In the answer, "0A H" represents the hexadecimal value of the content of the accumulator. The specific values for the interrupt masks are not mentioned in the question, so we can assume that enabling is represented by "1" and masking is represented by "0". Therefore, the binary representation of the interrupt masks would be 110, which is equal to 0A in hexadecimal.

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• 7.

### 8085 and 8086 have how many flags respectively?

• A.

5,8

• B.

5,7

• C.

5,9

• D.

5,6

C. 5,9
Explanation
The 8085 microprocessor has 5 flags, namely Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), and Carry (CY). On the other hand, the 8086 microprocessor has 9 flags, which include the same 5 flags as the 8085 along with Direction (D), Interrupt Enable (IE), Overflow (O), and Trap (T).

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• 8.

### 8086 supports pipelining because

• A.

It has EU and BIU separately

• B.

It supports MIN and MAX mode

• C.

BIU supports pre fetching

• D.

It is 16 bit microprocessor

C. BIU supports pre fetching
Explanation
The correct answer is "BIU supports pre fetching". The BIU (Bus Interface Unit) in the 8086 microprocessor is responsible for fetching instructions and data from memory. It supports pre-fetching, which means that it can fetch multiple instructions ahead of time and store them in a buffer. This allows the processor to overlap the fetching and execution of instructions, resulting in improved performance and increased throughput. By pre-fetching instructions, the pipeline can stay filled with instructions, reducing the idle time of the processor and increasing its efficiency.

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• 9.

### 8086 is 16 a bit microprocessor

• A.

Hence supports word length of 16 bit

• B.

Because it has 16 bit data bus

• C.

Because it has word length of 8 and data bus of 16 bit

• D.

None of the Options

C. Because it has word length of 8 and data bus of 16 bit
Explanation
The given answer is incorrect. The 8086 microprocessor is actually a 16-bit microprocessor, not 8-bit. It has a 16-bit word length and a 16-bit data bus. Therefore, the correct explanation would be: "8086 is a 16-bit microprocessor and supports a word length of 16 bits because it has a 16-bit data bus."

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• 10.

### 8086 has how many vectored interrupts?

• A.

5

• B.

4

• C.

12

• D.

None of the Options

C. 12
Explanation
The correct answer is 12 because the 8086 microprocessor has 12 vectored interrupts. Vectored interrupts are a type of interrupt where the interrupting device provides additional information to the processor about the interrupt, such as the specific address of the interrupt service routine. The 8086 microprocessor supports 12 different interrupt vectors, allowing for a wide range of interrupt-driven operations and device interactions.

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• 11.

### How many hardware interrupts support masking by more than 1 way?

• A.

5

• B.

4

• C.

2

• D.

3

C. 2
Explanation
There are two hardware interrupts that support masking by more than one way. This means that these interrupts can be disabled or enabled using multiple methods or techniques.

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• 12.

### EI and DI has instructiuon length of how many bytes?

• A.

1

• B.

2

• C.

3

• D.

None of the Options

A. 1
Explanation
EI and DI instructions have an instruction length of 1 byte. These instructions are used in assembly language programming to enable and disable interrupts, respectively. The 1-byte length indicates that these instructions occupy only a single memory location, making them efficient and compact.

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• 13.

### Why TRAP is edge and level sensitive?

• A.

Because to avoid trigeering by only level

• B.

To avoid false triggering because of noise

• C.

To avoid false triggering

• D.

None of the Options

B. To avoid false triggering because of noise
Explanation
TRAP is edge and level sensitive to avoid false triggering because of noise. By being both edge and level sensitive, the input signal must meet specific criteria in order to trigger an action. This helps to filter out any noise or unwanted signals that may cause false triggering. By requiring both an edge and a level change, the circuit can more accurately determine when a valid signal is present, reducing the chances of false triggering.

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• 14.

### In how many ways RST 5.5, RST 6.5 and RST 7.5 can be disabled?

• A.

1

• B.

2

• C.

3

• D.

4

C. 3
Explanation
The given question asks how many ways the items RST 5.5, RST 6.5, and RST 7.5 can be disabled. The answer is 3 because there are three items that can be disabled individually: RST 5.5, RST 6.5, and RST 7.5.

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• 15.

• A.

0A H

• B.

0B H

• C.

0C H

• D.

0D H

C. 0C H
• 16.

### RIM instruction is exceuted , RST 6.5 is pending , then what is the content of the accumulator?

• A.

10 H

• B.

20 H

• C.

30 H

• D.

40 H

B. 20 H
Explanation
The content of the accumulator would be 20 H. This is because the RIM instruction is executed before the RST 6.5 is pending. The RIM instruction reads the status of the interrupt mask flip-flops and stores it in the accumulator. Therefore, the content of the accumulator would be the value read from the interrupt mask flip-flops, which in this case is 20 H.

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• 17.

### What is the use of TRAP Interrupt?

• A.

• B.

IO Interfacing

• C.

DMA Request

• D.

Interrupt in Power Failure

D. Interrupt in Power Failure
Explanation
The use of TRAP Interrupt is to handle interrupt requests caused by power failures. When a power failure occurs, the TRAP Interrupt is triggered and the system can perform necessary actions to save data, shut down safely, or initiate a backup power source. This interrupt is crucial in preventing data loss or system damage during unexpected power outages.

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• 18.

### RST 7.5 is

• A.

• B.

• C.

• D.

Maskable , Hardwired, Vectored, Level Sensitive

• 19.

### How many interrupts SIM and DI disable respectively?

• A.

3,4

• B.

0-3,4

• C.

2,4

• D.

3,3

B. 0-3,4
Explanation
SIM (Serial Interface Module) is a peripheral device used for serial communication. It can generate interrupts for various events such as data reception, transmission, or error conditions. In this question, the answer "0-3,4" suggests that SIM can disable interrupts from interrupt sources 0, 1, 2, 3, and 4. On the other hand, DI (Digital Input) is a general term and does not specifically refer to a particular device or interrupt source. Therefore, it does not disable any interrupts.

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• 20.

### Which interrupt requires a separate programmable interrupt controller?

• A.

INTR

• B.

TRAP

• C.

RST 7.5

• D.

RST 6.5

A. INTR
Explanation
The interrupt that requires a separate programmable interrupt controller is INTR. This interrupt signal is used to request an interrupt from an external device. The programmable interrupt controller is responsible for managing and prioritizing different interrupt requests from various devices. By using a separate programmable interrupt controller, the system can efficiently handle and respond to multiple interrupt requests simultaneously.

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• 21.

### What is the role of D4 in SIM instruction?

• A.

Don't care

• B.

Serial I/O

• C.

• D.

Clearing D F/F Associated with RST 7.5

D. Clearing D F/F Associated with RST 7.5
Explanation
The role of D4 in the SIM instruction is to clear the D flip-flop associated with the RST 7.5 interrupt. This means that when the SIM instruction is executed, it will reset the D flip-flop, disabling the RST 7.5 interrupt. The other options, such as "Don't care," "Serial I/O," and "Masking 7.5," do not accurately describe the role of D4 in the SIM instruction.

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• 22.

### Can trap be disabled?

• A.

Yes by software

• B.

Yes by Hardwire

• C.

No

• D.

Yes by Softwire and Hardwire

D. Yes by Softwire and Hardwire
Explanation
The correct answer is "Yes by Softwire and Hardwire". This means that traps can be disabled using both software and hardware methods. Software methods involve modifying the code or settings of a system to disable the traps, while hardware methods involve physically disconnecting or disabling the trap mechanism. By combining both software and hardware approaches, traps can be effectively disabled.

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• 23.

### Which Interrupt require polling?

• A.

None for 8085

• B.

TRAP

• C.

All except TRAP

• D.

INTR

D. INTR
Explanation
The correct answer is INTR. In the 8085 microprocessor, the INTR interrupt requires polling. Polling is a method used to check if an interrupt request is pending by continuously checking a specific flag or condition. The INTR interrupt is a maskable interrupt that can be enabled or disabled by the programmer. When enabled, the microprocessor checks the INTR pin periodically to see if an interrupt request is pending. If a request is detected, the microprocessor suspends its current operation and jumps to the interrupt service routine to handle the interrupt.

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• Current Version
• Mar 22, 2023
Quiz Edited by
ProProfs Editorial Team
• Oct 05, 2015
Quiz Created by
Catherine Halcomb

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