MIS 502 Ch 4 Quiz Drilled Down -

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  • 1/31 Questions

    In many CPUs, a register called the program status word (PSW) stores condition codes, including those representing processing errors and the results of comparison operations.

    • True
    • False
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About This Quiz

This MIS 502 CH 4 quiz evaluates understanding of CPU functions, RISC processors, and binary arithmetic in computer systems. It tests knowledge on instruction sets, branch prediction, and error handling, preparing learners for advanced topics in management information systems.

MIS 502 Ch 4 Quiz Drilled Down - - Quiz

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  • 2. 

    The components of an instruction are its op code and one or more ____.

    • Boolean values

    • Operands

    Correct Answer
    A. Operands
    Explanation
    An instruction consists of an operation code (op code) which represents the specific operation to be performed, and one or more operands. Operands are the values or variables on which the operation is performed. They provide the necessary data for the operation to be executed correctly. Therefore, the correct answer is operands.

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  • 3. 

    One hertz is 1 clock cycle per second.

    • True

    • False

    Correct Answer
    A. True
    Explanation
    One hertz is a unit of frequency that represents one cycle per second. In other words, it measures the number of times an event (such as a clock cycle) occurs in one second. Therefore, the statement "One hertz is 1 clock cycle per second" is true.

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  • 4. 

    In many CPUs, a register called the ____ stores condition codes, including those representing processing errors and the results of comparison operations.

    • Program status word

    • Instruction register

    Correct Answer
    A. Program status word
    Explanation
    The program status word is a register in many CPUs that stores condition codes. These condition codes represent processing errors and the results of comparison operations. This register allows the CPU to keep track of the status of the program being executed and make decisions based on these conditions. It is an essential component for error handling and control flow in the CPU.

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  • 5. 

    The ____ tests the bit values in the source location and places copies of those values in the destination location.

    • LOAD

    • MOVE

    • STORE

    • ADD

    Correct Answer
    A. MOVE
    Explanation
    The correct answer is MOVE because it is the operation that tests the bit values in the source location and places copies of those values in the destination location. LOAD is used to load data from memory into a register, STORE is used to store data from a register into memory, and ADD is used to perform addition operations. Therefore, MOVE is the most suitable option for the given scenario.

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  • 6. 

    A(n) MOVE instruction copies data bits to storage locations.

    • True

    • False

    Correct Answer
    A. True
    Explanation
    A MOVE instruction is a type of instruction in computer programming that is used to copy data bits from one location to another. It is commonly used to transfer data between registers or memory locations. Therefore, the statement that a MOVE instruction copies data bits to storage locations is true.

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  • 7. 

    The CPU always determines the next instruction to fetch by looking in the instruction pointer.

    • True

    • False

    Correct Answer
    A. True
    Explanation
    The explanation for the given correct answer is that the CPU uses the instruction pointer to keep track of the memory address of the next instruction to be executed. It fetches the instruction from that memory address and proceeds to execute it. Therefore, it can be concluded that the CPU always determines the next instruction to fetch by looking in the instruction pointer.

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  • 8. 

    A RISC CPU typically uses variable length instructions and has a large instruction set.

    • True

    • False

    Correct Answer
    A. False
    Explanation
    A RISC CPU typically uses fixed-length instructions and has a small instruction set.

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  • 9. 

    Shifting a binary value one bit to the right multiplies the value by 2.

    • True

    • False

    Correct Answer
    A. False
    Explanation
    Shifting a binary value one bit to the right does not multiply the value by 2. Instead, it divides the value by 2. Shifting a binary value to the right by one bit is equivalent to performing an integer division by 2, which results in the value being halved. Therefore, the statement is false.

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  • 10. 

    A(n) ____ is a unit of data that contains a fixed number of bytes or bits.

    • Word

    • String

    • Character

    • PSW

    Correct Answer
    A. Word
    Explanation
    A word is a unit of data that contains a fixed number of bytes or bits. It is commonly used in computer programming to represent a specific amount of data storage. A word can vary in size depending on the computer architecture, but it typically refers to a group of 2, 4, or 8 bytes. It is used to store and manipulate data such as numbers, characters, or memory addresses.

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  • 11. 

    A(n) load instruction copies data from one memory location to another.

    • True

    • False

    Correct Answer
    A. False
    Explanation
    A load instruction is a type of instruction that retrieves data from memory and loads it into a register, rather than copying it from one memory location to another. Therefore, the given statement is false.

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  • 12. 

    Which of the following CPU performance enhancement methods can improve the efficiency of pipelining?

    • Branch prediction

    • Speculative execution

    • Simultaneous execution of both branches

    • All of the above

    Correct Answer
    A. All of the above
    Explanation
    All of the mentioned methods can improve the efficiency of pipelining. Branch prediction is a technique used to predict the outcome of a branch instruction, allowing the pipeline to continue processing instructions without waiting for the branch instruction to be resolved. Speculative execution involves executing instructions ahead of time, assuming the outcome of a branch prediction, to avoid pipeline stalls. Simultaneous execution of both branches refers to executing instructions from both branches of a conditional branch simultaneously, further improving pipeline efficiency. Therefore, all of these methods contribute to enhancing the efficiency of pipelining.

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  • 13. 

    Which of the following causes the processor to depart from sequential instruction order?

    • BRANCH

    • MOVE

    • SHIFT

    • ADD

    Correct Answer
    A. BRANCH
    Explanation
    A branch instruction causes the processor to depart from sequential instruction order by redirecting the program execution to a different location in the code. This allows for decision-making and looping in the program, as the processor can jump to different sections of the code based on certain conditions or loops. This is essential for implementing control flow in programs and executing different sets of instructions based on specific conditions.

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  • 14. 

    Current fabrication technology is capable of squeezing ____ transistors onto a wafer of silicon approximately one square centimeter in size.

    • Under 100 million

    • Approximately 100 million

    • Approximately 200 million

    • Over 300 million

    Correct Answer
    A. Over 300 million
    Explanation
    The given answer states that current fabrication technology is capable of squeezing over 300 million transistors onto a wafer of silicon approximately one square centimeter in size. This implies that the technology has advanced to a level where it can accommodate a very high number of transistors on a small surface area, indicating significant progress in miniaturization and density of transistors.

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  • 15. 

    A CPU with multiple execution units can more efficiently evaluate the formula (((a + b) x (c + d)) - ((e + f) / (g + h))).

    • True

    • False

    Correct Answer
    A. True
    Explanation
    A CPU with multiple execution units can more efficiently evaluate the given formula because the multiple execution units allow for parallel processing, which means that different parts of the formula can be computed simultaneously. This reduces the overall execution time and improves efficiency.

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  • 16. 

    What law predicts that the cost of a manufacturing plant and equipment for the latest generation of microprocessors doubles every four years?

    • Moore’s Law

    • Rock’s Law

    • Shannon’s Law

    • Gallium’s Law

    Correct Answer
    A. Rock’s Law
    Explanation
    Rock's Law predicts that the cost of a manufacturing plant and equipment for the latest generation of microprocessors doubles every four years. This law is named after Arthur Rock, an American businessman and venture capitalist who formulated this principle. According to Rock's Law, as technology advances and new generations of microprocessors are developed, the cost of producing them increases exponentially. This can be attributed to the increasing complexity and sophistication of the manufacturing processes and equipment required to produce these advanced microprocessors.

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  • 17. 

    If A and B are two's complement values, the result of subtracting B from A can be computed by XORing A with a string of 1-bits, ADDing one to the result, then ADDing B.

    • True

    • False

    Correct Answer
    A. False
    Explanation
    The given statement is false. The result of subtracting B from A can be computed by taking the two's complement of B and then adding it to A, not by XORing A with a string of 1-bits, adding one to the result, and then adding B.

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  • 18. 

    The word size of a processor should be ____ the width of the data bus for maximal performance.

    • Less than

    • No more than

    • At least as large as

    • Greater than

    Correct Answer
    A. At least as large as
    Explanation
    The word size of a processor should be at least as large as the width of the data bus for maximal performance. This is because the word size determines the amount of data that the processor can process in a single operation, while the data bus is responsible for transferring data between the processor and other components. If the word size is smaller than the data bus width, it would result in multiple operations to transfer a single piece of data, leading to slower performance. Therefore, having a word size at least as large as the data bus width ensures optimal performance.

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  • 19. 

    The term pipelining describes instruction execution beyond a conditional branch instruction before the branch condition value is know with certainty.

    • True

    • False

    Correct Answer
    A. False
    Explanation
    Pipelining does not involve executing instructions beyond a conditional branch instruction before the branch condition value is known with certainty. In pipelining, instructions are executed in parallel stages, but the branch instruction is typically resolved in the pipeline before executing subsequent instructions. Therefore, the given statement is false.

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  • 20. 

    A(n) ____ is a template that specifies the number of operands and the position and length of the op code and operands.

    • Reduced Instruction Set

    • PSW

    • Heat sink

    • Instruction format

    Correct Answer
    A. Instruction format
    Explanation
    An instruction format is a template that specifies the number of operands and the position and length of the op code and operands. It provides a structure for encoding and decoding instructions in a computer system. By following the instruction format, the processor can correctly interpret and execute the instructions provided by the program. This format ensures consistency and standardization in the way instructions are represented and processed, allowing for efficient and accurate execution of programs.

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  • 21. 

    A reduced instruction set computing (RISC) processor does not directly implement instructions that combine data movement and manipulation.

    • True

    • False

    Correct Answer
    A. True
    Explanation
    A reduced instruction set computing (RISC) processor is designed to simplify the instruction set architecture by reducing the number of instructions and focusing on simpler instructions that can be executed quickly. This means that a RISC processor does not directly implement instructions that combine both data movement and manipulation. Instead, it separates these tasks into separate instructions, allowing for more efficient and streamlined execution of instructions. Therefore, the statement "A reduced instruction set computing (RISC) processor does not directly implement instructions that combine data movement and manipulation" is true.

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  • 22. 

    With respect to two's complement values, which of the following is NOT a complex instruction than can be implemented by a sequence of more primitive instructions?

    • Divide

    • Add

    Correct Answer
    A. Add
    Explanation
    The given question is asking which of the following is NOT a complex instruction that can be implemented by a sequence of more primitive instructions. The correct answer is "Add." This means that the "Add" instruction is not a complex instruction and can be implemented directly without the need for a sequence of more primitive instructions.

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  • 23. 

    How does the CPU know from which memory location to fetch its next instruction?

    • It doesn't, memory supplies it automatically

    • It looks in the instruction pointer

    • The output of the last instruction is the address of the next instruction

    • It increments the address of the previous instruction

    Correct Answer
    A. It increments the address of the previous instruction
    Explanation
    The CPU knows from which memory location to fetch its next instruction by incrementing the address of the previous instruction. This means that after executing an instruction, the CPU increments the program counter, which points to the memory address of the next instruction to be fetched. By incrementing this address, the CPU ensures that it fetches the next instruction in sequence.

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  • 24. 

    A CPU with multiple execution units can more efficiently evaluate the formula ((((a + b) x c) - d) / e).

    • True

    • False

    Correct Answer
    A. False
    Explanation
    A CPU with multiple execution units does not necessarily make the evaluation of the formula ((((a + b) x c) - d) / e) more efficient. The efficiency of evaluating this formula depends on various factors such as the architecture of the CPU, the complexity of the formula, and the specific operations involved. Multiple execution units can potentially improve performance in certain scenarios, but it is not a guarantee that the formula will be evaluated more efficiently.

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  • 25. 

    A CPU typically implements multiple instruction formats to account for differences among instructions in the number and type of op codes.

    • True

    • False

    Correct Answer
    A. False
    Explanation
    A CPU typically implements multiple instruction formats to account for differences among instructions in the number and type of op codes. This statement is false. A CPU typically implements a single instruction format that is designed to handle all instructions. The instruction format includes fields for the opcode, operands, and any additional data required for the instruction. The CPU decodes the opcode to determine the specific operation to be performed and uses the other fields to fetch the operands and execute the instruction.

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  • 26. 

    The components of an instruction are its operand and one or more op codes.

    • True

    • False

    Correct Answer
    A. False
    Explanation
    The components of an instruction are not just its operand and one or more op codes. An instruction typically consists of an opcode, which specifies the operation to be performed, and one or more operands, which are the data on which the operation is to be performed. Therefore, the given statement is false.

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  • 27. 

    A CPU typically implements multiple instruction formats to account for differences among instructions in the number and type of op codes.

    • True

    • False

    Correct Answer
    A. False
    Explanation
    A CPU typically implements a single instruction format to ensure consistency and efficiency in executing instructions. Having multiple instruction formats would introduce complexity and make it difficult to design and optimize the CPU architecture. Therefore, the statement that a CPU typically implements multiple instruction formats is false.

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  • 28. 

    A transistor is an electrical circuit that implements a boolean or other primitive processing function on single bit inputs.

    • True

    • False

    Correct Answer
    A. False
    Explanation
    The given statement is false. A transistor is not an electrical circuit that implements a boolean or other primitive processing function on single bit inputs. Instead, a transistor is a semiconductor device that can amplify or switch electronic signals and electrical power. It is a fundamental building block of modern electronic devices and is used in various applications such as computers, televisions, and radios.

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  • 29. 

    Branch prediction improves CPU performance by dividing instruction execution into stages and overlapping execution of multiple instructions in different stages.

    • True

    • False

    Correct Answer
    A. False
    Explanation
    Branch prediction does not improve CPU performance by dividing instruction execution into stages and overlapping execution of multiple instructions in different stages. Instead, branch prediction is a technique used by CPUs to guess the outcome of a branch instruction before it is actually executed, in order to speculatively execute instructions and minimize the impact of branch delays.

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  • 30. 

    Doubling word size ____ CPU transistor count.

    • Less than doubles

    • Doubles

    • More than doubles

    • Has no relationship to

    Correct Answer
    A. More than doubles
    Explanation
    When the word size of a CPU doubles, it means that the CPU can now store and process twice as much data in a single operation. In order to accommodate this increase in word size, the transistor count of the CPU needs to increase as well. However, the answer "more than doubles" suggests that the increase in transistor count is greater than just doubling. This implies that there may be additional transistors required to support the increased word size and potentially other enhancements or improvements to the CPU architecture.

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  • 31. 

    The address of the next instruction to be fetched by the CPU is held in the instruction register.

    • True

    • False

    Correct Answer
    A. False
    Explanation
    The address of the next instruction to be fetched by the CPU is not held in the instruction register. The instruction register holds the current instruction being executed by the CPU. The address of the next instruction to be fetched is typically held in a separate register called the program counter.

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  • Current Version
  • Mar 21, 2023
    Quiz Edited by
    ProProfs Editorial Team
  • Oct 12, 2010
    Quiz Created by
    Olkaz
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