This test goes along with chapter 7 of our Comptia A+ book.
DDR doubles the data rate of memory by processing data when the beat of the clock rises and again when it falls.
DDR runs more slowly than regular SDRAM.
DDR uses 168 pins.
DDR improves on DDR2.
It makes the parity bit a 1 or a 0 to make the number of 1s in the 9 bits even.
A parity error occurs only when there is an odd number of bits.
It makes the ninth or parity bit either a 1 or a 0 to make the number of 1s in the 9 bits odd.
Newer DRAM systems also us odd parity error checking.
Both features refer to the size of the memory module.
RAS Latency is used more than CAS Latency.
It takes four or five clock cycles to read or write data.
Both features refer to the number of clock cycles it takes to write or read a column or row of data off a memory module.
Memory controller hub
Error correcting code
DDR and DDR2
DRAM and SRAM
Parity and ECC
ROM and RAM
the voltage used by the module
The module as registered, buffered, or unbuffered
The manufacturer of the module
The type of memory technology the module uses
Here's an interesting quiz for you.