Cao Online Test
.
- 1.
Instruction decoder of a CPU
- A.
Decodes the instruction and carries out the arithmetic and logical operations.
- B.
Decodes the instruction and generates the corresponding control signals.
- C.
Decodes and stores the instruction currently being decoded.
- D.
None of the above
Correct Answer
B. Decodes the instruction and generates the corresponding control signals. -
- 2.
The instruction ADD R1, 30FF is of
- A.
A 3-address instruction format
- B.
A 2-address instruction format
- C.
A 1-address instruction format
- D.
A 0-address instruction format
Correct Answer
B. A 2-address instruction format -
- 3.
An instruction ADD 30FF
- A.
Adds 30FF to the value in Accumulator and stores the sum in the memory location 30FF
- B.
Adds 30FF to the value in Accumulator and stores the sum in Accumulator
- C.
Adds the value in memory location 30FF to the value in Accumulator and stores the sum in Accumulator
- D.
None of the above
Correct Answer
C. Adds the value in memory location 30FF to the value in Accumulator and stores the sum in Accumulator -
- 4.
- Which of the following options represents the correct matching?
- A.
1->A; 2->D; 3->C; 4->B;
- B.
1->D; 2->A; 3->B; 4->C;
- C.
1->D; 2->A; 3->C; 4->B;
- D.
1->A; 2->D; 3->B; 4->C;
Correct Answer
B. 1->D; 2->A; 3->B; 4->C; - 5.
LOAD R2, 30FF is
- A.
Arithmetic and Logical instruction
- B.
Control instruction
- C.
Data transfer instruction
- D.
None of the above
Correct Answer
C. Data transfer instruction -
- 6.
MBR in a CPU is
- A.
A special purpose register used to provide the memory address
- B.
A special purpose register used to store the instructions
- C.
A special purpose register used for data transfer
- D.
A special purpose register used to store the address of the next instruction
Correct Answer
C. A special purpose register used for data transfer -
- 7.
The module which is not a part of the CPU is
- A.
Arithmetic processing unit
- B.
General purpose registers
- C.
Main memory
- D.
Control unit
Correct Answer
C. Main memory -
- 8.
In which stage of the instruction cycle, the address stored in the PC is retrieved?
- A.
Instruction fetch
- B.
Decode
- C.
Execute
- D.
Interrupt
Correct Answer
A. Instruction fetch -
- 9.
In which of the following addressing mode, the memory location of an operand is specified in the instruction?
- A.
Immediate addressing mode
- B.
Direct addressing mode
- C.
Indirect addressing mode
- D.
None of these
Correct Answer
B. Direct addressing mode -
- 10.
The register which holds the address of the location to or from which data are to be transferred is called
- A.
Memory data register
- B.
Instruction register
- C.
Program counter
- D.
Memory address register
Correct Answer
D. Memory address register -
- 11.
During a fetch-execute cycle, the memory address of the instruction to be fetched is transmitted from the program counter to the RAM through ____________.
- A.
Data bus
- B.
Address bus
- C.
Control bus
- D.
either data bus or address bus
Correct Answer
B. Address bus -
- 12.
If the last operation performed on a computer with an 8-bit word was an addition in which the two operands were 00000010 and 00000011, what would be the value of the following flags? Assume that, the operands are stored in sign-magnitude form.
- Carry
- Zero
- Overflow
- Sign
- Even Parity
- Half-Carry
- A.
0, 0, 1, 0, 1, 0
- B.
0, 1, 0, 0, 1, 0
- C.
0, 0, 0, 0, 1, 0
- D.
0, 0, 1, 0, 0, 0
Correct Answer
C. 0, 0, 0, 0, 1, 0 - 13.
Indicate which of the following logic gates can be used to realize all possible combinational logic functions:
- A.
OR gates only
- B.
NAND gates only
- C.
EX-OR gates only
- D.
NOR gates only
Correct Answer
B. NAND gates only -
- 14.
A processor that has a carry, overflow, and sign flag bits as part of its program status word (PSW) performs addition of the following 2’s complement number 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be:
- A.
1, 1, 0
- B.
1, 0, 0
- C.
0, 1, 0
- D.
1, 0, 1
Correct Answer
B. 1, 0, 0 -
- 15.
SRAMs generally have faster access time than DRAMs. DRAMs are less expensive and smaller than SRAMs
- A.
True
- B.
False
Correct Answer
A. True -
- 16.
A bus consisting of 8 lines can
- A.
Transmit 8-byte unit of data
- B.
Transmit 8-bit unit of data
- C.
Transmit 256 bit unit of data
- D.
None of the above
Correct Answer
B. Transmit 8-bit unit of data -
- 17.
Control unit sends control signals to different modules to
- A.
Synchronise the modules
- B.
Store the status of the processor
- C.
Select the functionality of the modules
- D.
Decode the instruction
Correct Answer
C. Select the functionality of the modules -
- 18.
The 4 micro-operations of an instruction fetch cycle are shown below. Which of the following clock cycle grouping is possible?
- A.
t1 and t2
- B.
t2 and t3
- C.
t2 and t4
- D.
All of the above
Correct Answer
B. t2 and t3 -
- 19.
For a CPU with single bus organisation, as shown below, the control steps for completely executing an instruction “LOAD R1, #32” (with immediate addressing mode) are:
- A.
1) PCout , MARin, Read, Select=0, Add, Zin 2) Zout , PCin , WMFC 3) MDRout, IRin 4) IRout, R1in
- B.
1)PCout , MARin, Read, Select=0, Add, Zin 2) Zout , PCin , WMFC 3) MDRout, IRin 4) IRout, MARin, Read 5) WMFC 6) MDRout, Yin, Select=1, Add 7) R1out, Zin 8) Zout, R1in
- C.
1) PCout , MARin, Read, Select=0, Add, Zin 2) Zout , PCin , Yin, WMFC 3) MDRout, IRin 4) Offset-field-of-IRout, Select=1, Add, Zin, If Zero Flag!=0 then END 5) Zout, PCin
- D.
None of the above
Correct Answer
A. 1) PCout , MARin, Read, Select=0, Add, Zin 2) Zout , PCin , WMFC 3) MDRout, IRin 4) IRout, R1in -
- 20.
For a CPU with single bus organisation, the control steps for completely executing an instruction “ADD R1, M” (where, M is a memory location) (with direct addressing mode) are:
- A.
1) PCout , MARin, Read, Select=0, Add, Zin 2) Zout , PCin , WMFC 3) MDRout, IRin 4) IRout, R1in
- B.
1) PCout , MARin, Read, Select=0, Add, Zin 2) Zout , PCin , Yin, WMFC 3) MDRout, IRin 4) Offset-field-of-IRout, Select=1, Add, Zin, If Zero Flag!=0 then END 5) Zout, PCin
- C.
1)PCout , MARin, Read, Select=0, Add, Zin 2) Zout , PCin , WMFC 3) MDRout, IRin 4) IRout, MARin, Read 5) WMFC 6) MDRout, Yin, Select=1, Add 7) R1out, Zin 8) Zout, R1in
- D.
None of the above
Correct Answer
C. 1)PCout , MARin, Read, Select=0, Add, Zin 2) Zout , PCin , WMFC 3) MDRout, IRin 4) IRout, MARin, Read 5) WMFC 6) MDRout, Yin, Select=1, Add 7) R1out, Zin 8) Zout, R1in -
- 21.
In computers, subtraction is carried out generally by
- A.
1's complement method
- B.
2's complement method
- C.
 signed magnitude method
- D.
BCD subtraction method
Correct Answer
B. 2's complement method -
- 22.
Which number is said to be normalized if the more significant position of the mantissa contains a non zero digit:
- A.
Binary point number
- B.
Mantissa point number
- C.
Floating point number
- D.
None of these
Correct Answer
C. Floating point number -
- 23.
The computer architecture aimed at reducing the time of execution of instructions is ________
- A.
CISC
- B.
RISC
- C.
ISA
- D.
ANNA
Correct Answer
B. RISC -
- 24.
The RISC processor has a more complicated design than CISC.
- A.
True
- B.
False
Correct Answer
B. False -
- 25.
To increase the speed of memory access in pipelining, we make use of _______
- A.
Special memory locations
- B.
Special purpose registers
- C.
Cache
- D.
Buffers
Correct Answer
C. Cache -
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Mar 13, 2018Quiz Edited by
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Mar 13, 2018Quiz Created by
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