SMPS - Current Mode Control

11 Questions | Total Attempts: 171

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SMPS - Current Mode Control - Quiz

This quiz is written to enhance the knowledge and skills of any engineer having a passion towards switchmode power supply technology. This quiz is the first in a series of quizzes that will be put up on this site, to cover various aspects of design and technology, in the field of Power Electronics Design, with a larger emphasis on high frequency switch mode power conversion. The scope shall range from theoretical concepts that are taught in colleges, to practical implementations adopted by the industry. The quiz is targetted for both entry level and experienced power supply designers.


Questions and Answers
  • 1. 
    Given a choice between NMOS versus PMOS device,  both having the same RDSON, The most important advantage the NMOS device has as compared to PMOS,  when used in high side drive applications is :-
    • A. 

      The junction to case thermal resistance is lower

    • B. 

      The control drive circuit is simpler

    • C. 

      Lower Switching Losses

    • D. 

      Lower conduction losses

  • 2. 
    The main disadvantage of synchronous rectifiers over non-synchronous rectifiers is :-
    • A. 

      Higher switching noise at the output

    • B. 

      Lower Efficiency

    • C. 

      Lower Maximum operating frequency

    • D. 

      Higher cost

  • 3. 
    The most significant advantage of  Peak CMC over VMC (from a control loop point of view) is :-
    • A. 

      RHP Zero is eliminated

    • B. 

      Stability is easier to achieve over transitions from CCM to DCM and vice versa

    • C. 

      Inherent feedforward compensation

    • D. 

      Control to Output gain is higher at low frequencies

  • 4. 
    In which of the following applications,  is Voltage Mode Control preferred over Peak Current Mode Control
    • A. 

      The power supply output is to be a current source.

    • B. 

      Very fast dynamic response is needed.

    • C. 

      Modular applications where parallelability with load sharing is required.

    • D. 

      Application uses a push-pull transformer.

    • E. 

      Application calls for operation from zero load or very low minimum load

  • 5. 
    When using Peak CMC Buck converter at  extremely high switching frequencies,  which of the below would be the most dominant factor that affects proper circuit operation.
    • A. 

      Time delays caused by the R-C filter used to sense the current.

    • B. 

      Noise on the input line.

    • C. 

      ESR of the output capacitor

    • D. 

      ESR of the output inductor.

  • 6. 
    In Peak CMC , practically,  the freedom from subharmonic oscillations, along with reasonable line regulation,  can be achieved by :-
    • A. 

      Ensuring that compensating slope has a gradient equal to the inductor current downslope.

    • B. 

      Ensuring that compensating slope has a gradient little > half the inductor current downslope.

    • C. 

      Ensuring that compensating slope has a gradient equal to twice the inductor current downslope.

    • D. 

      By not having any slope compensation.

  • 7. 
    In Peak CMC , perfect rejection of duty cycle disturbances,  within one cycle can be achieved by :-
    • A. 

      Ensuring that compensating slope has a gradient little > half the inductor current downslope.

    • B. 

      Ensuring that compensating slope has a gradient equal to twice the inductor current downslope.

    • C. 

      By not having any slope compensation.

    • D. 

      Ensuring that compensating slope has a gradient equal to the inductor current downslope

  • 8. 
    In practical functioning Peak CMC forward converters,  the bandwidth of the (Output Voltage to Inductor Current) feedback loop is typically :-
    • A. 

      2 to 3 times switching frequency

    • B. 

      Greater than 2/3 times switching frequency

    • C. 

      1/6 to 2/3 times switching frequency

    • D. 

      Less than 2/3 times switching frequency.

  • 9. 
    For a  Peak CMC Buck Converter variable output voltage power supply,  the most significant factor that limits the achievable minimum output voltage is :-
    • A. 

      The ESR of the series output inductor

    • B. 

      Value of the minimum input line voltage

    • C. 

      Time delays caused by the R-C filter used to sense the current.

    • D. 

      Turns ratio of the transformer

  • 10. 
    In Peak CMC ,  duty cycle modulation is achieved by :-
    • A. 

      Controlling the turn-on event of the power switch

    • B. 

      Controlling the turn-off event of the power switch

    • C. 

      Controlling the switching frequency

    • D. 

      Controlling the reference voltage input to the voltage error amplifier

  • 11. 
    For a  Valley CMC Buck Converter variable output voltage power supply,  the most significant factor that limits the achievable maximum output voltage is :-
    • A. 

      The ESR of the series output inductor

    • B. 

      Value of the maximum input line voltage

    • C. 

      Turns ratio of the transformer

    • D. 

      Time delays caused by the R-C filter used to sense the current.

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