SMPS - Current Mode Control

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| By Professor63
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Quizzes Created: 1 | Total Attempts: 192
Questions: 11 | Attempts: 192

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SMPS - Current Mode Control - Quiz

This quiz is written to enhance the knowledge and skills of any engineer having a passion towards switchmode power supply technology. This quiz is the first in a series of quizzes that will be put up on this site, to cover various aspects of design and technology, in the field of Power Electronics Design, with a larger emphasis on high frequency switch mode power conversion. The scope shall range from theoretical concepts that are taught in colleges, to practical implementations adopted by the industry. The quiz is targetted for both entry level Read moreand experienced power supply designers.


Questions and Answers
  • 1. 

    Given a choice between NMOS versus PMOS device,  both having the same RDSON, The most important advantage the NMOS device has as compared to PMOS,  when used in high side drive applications is :-

    • A.

      The junction to case thermal resistance is lower

    • B.

      The control drive circuit is simpler

    • C.

      Lower Switching Losses

    • D.

      Lower conduction losses

    Correct Answer
    C. Lower Switching Losses
    Explanation
    For the same RDSON, NMOS has a lower gate charge requirement, and hence lower switching losses.

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  • 2. 

    The main disadvantage of synchronous rectifiers over non-synchronous rectifiers is :-

    • A.

      Higher switching noise at the output

    • B.

      Lower Efficiency

    • C.

      Lower Maximum operating frequency

    • D.

      Higher cost

    Correct Answer
    C. Lower Maximum operating frequency
    Explanation
    Synchronous rectifiers have a main disadvantage of lower maximum operating frequency compared to non-synchronous rectifiers. This means that synchronous rectifiers are limited in terms of the highest frequency at which they can operate efficiently. This limitation can impact the overall performance and speed of the rectifier system.

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  • 3. 

    The most significant advantage of  Peak CMC over VMC (from a control loop point of view) is :-

    • A.

      RHP Zero is eliminated

    • B.

      Stability is easier to achieve over transitions from CCM to DCM and vice versa

    • C.

      Inherent feedforward compensation

    • D.

      Control to Output gain is higher at low frequencies

    Correct Answer
    B. Stability is easier to achieve over transitions from CCM to DCM and vice versa
    Explanation
    Stability is easier to achieve over transitions from CCM to DCM and vice versa. This means that when transitioning between Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) in a control loop, it is easier to maintain stability with Peak Current Mode Control (CMC) compared to Voltage Mode Control (VMC). This advantage is significant because it ensures that the control loop remains stable and reliable during these transitions, which is crucial for the overall performance and operation of the system.

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  • 4. 

    In which of the following applications,  is Voltage Mode Control preferred over Peak Current Mode Control

    • A.

      The power supply output is to be a current source.

    • B.

      Very fast dynamic response is needed.

    • C.

      Modular applications where parallelability with load sharing is required.

    • D.

      Application uses a push-pull transformer.

    • E.

      Application calls for operation from zero load or very low minimum load

    Correct Answer
    E. Application calls for operation from zero load or very low minimum load
    Explanation
    Voltage Mode Control is preferred over Peak Current Mode Control when the application calls for operation from zero load or very low minimum load. In these scenarios, Voltage Mode Control is more suitable because it provides better regulation and stability at low loads compared to Peak Current Mode Control. With Voltage Mode Control, the power supply can maintain a constant voltage output even at very low loads, ensuring reliable operation. On the other hand, Peak Current Mode Control may struggle to provide accurate regulation and stability at such low loads, making it less preferable in this particular application.

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  • 5. 

    When using Peak CMC Buck converter at  extremely high switching frequencies,  which of the below would be the most dominant factor that affects proper circuit operation.

    • A.

      Time delays caused by the R-C filter used to sense the current.

    • B.

      Noise on the input line.

    • C.

      ESR of the output capacitor

    • D.

      ESR of the output inductor.

    Correct Answer
    A. Time delays caused by the R-C filter used to sense the current.
    Explanation
    When using a Peak CMC Buck converter at extremely high switching frequencies, the most dominant factor that affects proper circuit operation would be the time delays caused by the R-C filter used to sense the current. The R-C filter introduces a delay in the current sensing process, which can lead to inaccuracies in the feedback loop and affect the stability and performance of the converter. This delay becomes more significant at higher switching frequencies, making it the most influential factor in this scenario.

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  • 6. 

    In Peak CMC , practically,  the freedom from subharmonic oscillations, along with reasonable line regulation,  can be achieved by :-

    • A.

      Ensuring that compensating slope has a gradient equal to the inductor current downslope.

    • B.

      Ensuring that compensating slope has a gradient little > half the inductor current downslope.

    • C.

      Ensuring that compensating slope has a gradient equal to twice the inductor current downslope.

    • D.

      By not having any slope compensation.

    Correct Answer
    B. Ensuring that compensating slope has a gradient little > half the inductor current downslope.
    Explanation
    The correct answer is "Ensuring that compensating slope has a gradient little > half the inductor current downslope." This is because having a compensating slope with a gradient slightly greater than half the inductor current downslope helps to prevent subharmonic oscillations and ensures reasonable line regulation in Peak CMC. This means that the compensating slope should be steep enough to provide stability and prevent oscillations, but not too steep that it causes excessive line regulation.

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  • 7. 

    In Peak CMC , perfect rejection of duty cycle disturbances,  within one cycle can be achieved by :-

    • A.

      Ensuring that compensating slope has a gradient little > half the inductor current downslope.

    • B.

      Ensuring that compensating slope has a gradient equal to twice the inductor current downslope.

    • C.

      By not having any slope compensation.

    • D.

      Ensuring that compensating slope has a gradient equal to the inductor current downslope

    Correct Answer
    D. Ensuring that compensating slope has a gradient equal to the inductor current downslope
    Explanation
    To achieve perfect rejection of duty cycle disturbances within one cycle in Peak CMC, the compensating slope should have a gradient equal to the inductor current downslope. This means that the rate of change of the compensating slope should match the rate of change of the inductor current downslope. By doing so, the compensating slope can effectively counteract the disturbances and maintain a stable output.

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  • 8. 

    In practical functioning Peak CMC forward converters,  the bandwidth of the (Output Voltage to Inductor Current) feedback loop is typically :-

    • A.

      2 to 3 times switching frequency

    • B.

      Greater than 2/3 times switching frequency

    • C.

      1/6 to 2/3 times switching frequency

    • D.

      Less than 2/3 times switching frequency.

    Correct Answer
    C. 1/6 to 2/3 times switching frequency
    Explanation
    In practical functioning Peak CMC forward converters, the bandwidth of the (Output Voltage to Inductor Current) feedback loop is typically between 1/6 to 2/3 times the switching frequency. This means that the feedback loop can effectively respond to changes in the output voltage and adjust the inductor current accordingly within this frequency range. Operating within this bandwidth ensures stable and efficient operation of the converter.

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  • 9. 

    For a  Peak CMC Buck Converter variable output voltage power supply,  the most significant factor that limits the achievable minimum output voltage is :-

    • A.

      The ESR of the series output inductor

    • B.

      Value of the minimum input line voltage

    • C.

      Time delays caused by the R-C filter used to sense the current.

    • D.

      Turns ratio of the transformer

    Correct Answer
    C. Time delays caused by the R-C filter used to sense the current.
    Explanation
    The time delays caused by the R-C filter used to sense the current is the most significant factor that limits the achievable minimum output voltage in a Peak CMC Buck Converter variable output voltage power supply. This is because the R-C filter introduces a delay in sensing the current, which affects the control loop response and can lead to instability and poor regulation of the output voltage. The longer the time delay, the more difficult it becomes to achieve a low output voltage. Therefore, minimizing the time delays caused by the R-C filter is crucial for achieving a low minimum output voltage.

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  • 10. 

    In Peak CMC ,  duty cycle modulation is achieved by :-

    • A.

      Controlling the turn-on event of the power switch

    • B.

      Controlling the turn-off event of the power switch

    • C.

      Controlling the switching frequency

    • D.

      Controlling the reference voltage input to the voltage error amplifier

    Correct Answer
    B. Controlling the turn-off event of the power switch
    Explanation
    In Peak CMC, duty cycle modulation is achieved by controlling the turn-off event of the power switch. This means that the power switch is turned on for a certain period of time and then turned off for another period of time, creating a modulated duty cycle. By controlling the turn-off event, the duration of the off-time can be adjusted, which in turn affects the duty cycle. This modulation technique allows for precise control of the output voltage or current in a power converter circuit.

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  • 11. 

    For a  Valley CMC Buck Converter variable output voltage power supply,  the most significant factor that limits the achievable maximum output voltage is :-

    • A.

      The ESR of the series output inductor

    • B.

      Value of the maximum input line voltage

    • C.

      Turns ratio of the transformer

    • D.

      Time delays caused by the R-C filter used to sense the current.

    Correct Answer
    D. Time delays caused by the R-C filter used to sense the current.
    Explanation
    The most significant factor that limits the achievable maximum output voltage in a Valley CMC Buck Converter variable output voltage power supply is the time delays caused by the R-C filter used to sense the current. This is because the R-C filter introduces a delay in the feedback loop, affecting the control of the converter. The delay can cause instability in the system and limit the maximum output voltage that can be achieved. The other factors mentioned, such as the ESR of the series output inductor, the value of the maximum input line voltage, and the turns ratio of the transformer, may also have an impact on the converter's performance, but they are not as significant as the time delays caused by the R-C filter.

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  • Current Version
  • Mar 18, 2023
    Quiz Edited by
    ProProfs Editorial Team
  • Feb 27, 2009
    Quiz Created by
    Professor63

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