# Gibilisco: Field Effect Transistor Quiz

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Do you know anything about Gibilisco: Field Effect Transistor? Let's see how well you perform on our " Gibilisco: Field Effect Transistor Quiz." It is a transistor that employs an electric field to manage the current flow. It is contained by the changes in the surface potential caused by the binding of molecules. To ace this quiz, you will need to understand things like what a JFET is and what transconductance is. This quiz will show you how much you realize about the field-effect transistor. Good Luck!

• 1.

### The current through the channel of a JFET is directly affected by all of the following, except the

• A.

Drain voltage.

• B.

Transconductance.

• C.

Gate voltage.

• D.

Gate bias.

B. Transconductance.
Explanation
The current through the channel of a JFET is directly affected by the drain voltage, gate voltage, and gate bias. The transconductance of a JFET, on the other hand, is a measure of how much the drain current changes in response to a change in the gate-source voltage. It is not directly affecting the current through the channel.

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• 2.

### In an N-channel JFET, pinchoff occurs when the gate bias is

• A.

Small and positive.

• B.

Zero.

• C.

Small and negative.

• D.

Large and negative.

D. Large and negative.
Explanation
In an N-channel JFET, pinchoff occurs when the gate bias is large and negative. Pinchoff refers to the point where the channel between the source and drain is completely blocked, resulting in no current flow. In an N-channel JFET, a large negative gate bias creates a strong electric field that repels the majority charge carriers (electrons) away from the channel, effectively pinching it off and preventing current flow.

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• 3.

### The current consists mainly of holes when a JFET

• A.

Has a P-type channel.

• B.

Is forward-biased.

• C.

Is zero-biased.

• D.

Is reverse-biased.

A. Has a P-type channel.
Explanation
When a JFET has a P-type channel, it means that the majority charge carriers are holes. In this configuration, the JFET operates in depletion mode. When the JFET is forward-biased, it allows current to flow through the channel by reducing the depletion region. When it is zero-biased, there is no current flowing through the channel. When the JFET is reverse-biased, it increases the depletion region and blocks the current flow. Therefore, the correct answer is "is reverse-biased."

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• 4.

### A JFET might work better than a bipolar transistor in

• A.

A high-voltage rectifier.

• B.

A weak-signal RF amplifier.

• C.

A power-supply filter.

• D.

A power transformer.

B. A weak-signal RF amplifier.
Explanation
A JFET might work better than a bipolar transistor in a weak-signal RF amplifier because JFETs have a higher input impedance and lower noise levels compared to bipolar transistors. This makes them more suitable for amplifying weak signals at high frequencies without introducing additional noise or distortion. Additionally, JFETs have a wider bandwidth, allowing them to handle higher frequencies more effectively.

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• 5.

### In a P-channel JFET,

• A.

The drain is forward-biased.

• B.

The source-gate junction is forward-biased.

• C.

The drain is negative relative to the source.

• D.

The gate must be at dc ground.

C. The drain is negative relative to the source.
Explanation
In a P-channel JFET, the drain is negative relative to the source. This is because in a P-channel JFET, the channel is formed by the flow of positive charge carriers (holes) from the source to the drain. The gate voltage controls the depletion region between the source and the channel, and when the gate voltage is negative relative to the source, it creates an electric field that attracts the positive charge carriers towards the gate, allowing current to flow from the source to the drain. Therefore, the drain is negative relative to the source.

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• 6.

### A JFET is sometimes biased at or beyond pinchoff in

• A.

A power amplifier.

• B.

A rectifier.

• C.

A filter.

• D.

A weak-signal amplifier.

A. A power amplifier.
Explanation
A JFET (Junction Field-Effect Transistor) is sometimes biased at or beyond pinchoff in a power amplifier. This is because biasing the JFET at or beyond pinchoff allows for maximum amplification of the input signal. In a power amplifier, the goal is to amplify the input signal to a high power level, and biasing the JFET in this way helps achieve that.

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• 7.

### The gate of a JFET exhibits a

• A.

Forward bias.

• B.

High impedance.

• C.

Low reverse resistance.

• D.

Low avalanche voltage.

B. High impedance.
Explanation
The gate of a JFET exhibits a high impedance because it is designed to have a very small input current. This high impedance allows the JFET to act as a voltage-controlled device, meaning that small changes in voltage at the gate can result in larger changes in current through the device. This makes JFETs suitable for applications that require high input impedance, such as amplifiers and signal processing circuits.

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• 8.

### Which of the following conditions is not normally desirable in a JFET?

• A.

A conducting channel

• B.

Holes as the majority carriers

• C.

A forward-biased P-N junction

• D.

A high input impedance

C. A forward-biased P-N junction
Explanation
A forward-biased P-N junction is not normally desirable in a JFET because it can cause current to flow through the junction, reducing the effectiveness of the JFET as a voltage-controlled device. JFETs are designed to operate in the depletion mode, where a reverse-biased P-N junction creates a depletion region that controls the flow of current. Forward biasing the junction would disrupt this depletion region and allow current to flow even when it is not desired. Therefore, a forward-biased P-N junction is not desirable in a JFET.

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• 9.

### When a JFET is pinched off,

• A.

The value of dID/dEG is very large with no signal input.

• B.

The value of dID/dEG might vary considerably with no signal input.

• C.

The value of dID/dEG is negative with no signal input.

• D.

The value of dID/dEG is zero with no signal input.

D. The value of dID/dEG is zero with no signal input.
Explanation
When a JFET is pinched off, it means that the gate-to-source voltage (VGS) is equal to or greater than the pinch-off voltage (VP). In this state, the channel between the source and drain is completely closed, resulting in no current flow (ID). Therefore, the change in drain current (dID) with respect to the change in gate-to-source voltage (dEG) is zero, indicating that the value of dID/dEG is zero with no signal input.

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• 10.

### Transconductance is the ratio of

• A.

A change in drain voltage to a change in source voltage.

• B.

A change in drain current to a change in gate voltage.

• C.

A change in gate current to a change in source voltage.

• D.

A change in drain current to a change in drain voltage.

B. A change in drain current to a change in gate voltage.
Explanation
Transconductance is a measure of how much the drain current of a device changes in response to a change in the gate voltage. It quantifies the relationship between the input voltage (gate voltage) and the output current (drain current) in a field-effect transistor (FET). It is an important parameter in understanding the amplification and control characteristics of FETs.

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• 11.

### Characteristic curves for JFETs generally show

• A.

Drain voltage as a function of source current.

• B.

Drain current as a function of gate current.

• C.

Drain current as a function of drain voltage.

• D.

Drain voltage as a function of gate current.

C. Drain current as a function of drain voltage.
Explanation
The characteristic curves for JFETs generally show the relationship between the drain current and the drain voltage. These curves illustrate how the drain current changes as the drain voltage is varied. By plotting the drain current on the y-axis and the drain voltage on the x-axis, the characteristic curves provide valuable information about the behavior and performance of the JFET device.

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• 12.

### A disadvantage of MOS components is the fact that

• A.

They can be easily damaged by static electricity.

• B.

They need a high input voltage in order to amplify.

• C.

They draw large amounts of current.

• D.

They produce a great deal of heat.

A. They can be easily damaged by static electricity.
Explanation
MOS components, or Metal-Oxide-Semiconductor components, have a disadvantage of being easily damaged by static electricity. Static electricity can build up on surfaces and discharge when it comes into contact with the MOS component, causing damage to the delicate circuitry. This can lead to malfunctions or complete failure of the component. Therefore, it is important to handle MOS components with caution and take necessary precautions to prevent static electricity buildup and discharge.

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• 13.

### The input impedance of a MOSFET is

• A.

Lower than that of a JFET.

• B.

Lower than that of a bipolar transistor.

• C.

Between that of a bipolar transistor and a JFET.

• D.

Extremely high.

D. Extremely high.
Explanation
The input impedance of a MOSFET is extremely high compared to that of a JFET or a bipolar transistor. This is because the input impedance of a MOSFET is mainly determined by the gate-source junction, which has a very high resistance. As a result, MOSFETs are able to draw very little current from the input signal source, making them suitable for high impedance applications where minimum loading is required.

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• 14.

### A significant difference between MOSFETs and JFETs is the fact that

• A.

MOSFETs can handle a wider range of gate bias voltages.

• B.

MOSFETs can deliver greater output power.

• C.

MOSFETs are more rugged.

• D.

MOSFETs last longer.

A. MOSFETs can handle a wider range of gate bias voltages.
Explanation
MOSFETs and JFETs are both types of field-effect transistors, but one significant difference between them is that MOSFETs can handle a wider range of gate bias voltages. This means that MOSFETs can operate effectively with a broader range of input voltages applied to the gate terminal, allowing for more flexibility in their applications. JFETs, on the other hand, have a more limited range of gate bias voltages that they can handle.

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• 15.

### The channel in a zero-biased JFET is normally

• A.

Pinched off.

• B.

In a state of avalanche breakdown.

• C.

In a conducting state.

• D.

C. In a conducting state.
Explanation
In a zero-biased JFET (junction field-effect transistor), the channel refers to the region between the source and drain terminals. When the JFET is in a conducting state, it means that current can flow through this channel. This is achieved by applying a voltage to the gate terminal, which controls the conductivity of the channel. Therefore, the correct answer is "in a conducting state."

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• 16.

### When an enhancement-mode MOSFET is at zero bias,

• A.

The drain current is high with no signal.

• B.

The drain current fluctuates with no signal.

• C.

The drain current is low with no signal.

• D.

The drain current is zero with no signal.

D. The drain current is zero with no signal.
Explanation
When an enhancement-mode MOSFET is at zero bias, the drain current is zero with no signal. This is because the MOSFET is in its off state when there is no bias voltage applied to the gate terminal. In this state, the channel between the drain and source is not conducting and therefore no current flows through the drain terminal.

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• 17.

### An enhancement-mode MOSFET can be recognized in schematic diagrams by the presence of:

• A.

An arrow pointing inward.

• B.

A broken vertical line inside the circle.

• C.

An arrow pointing outward.

• D.

A solid vertical line inside the circle.

B. A broken vertical line inside the circle.
Explanation
An enhancement-mode MOSFET can be recognized in schematic diagrams by the presence of a broken vertical line inside the circle. This broken line represents the absence of a conducting channel between the source and drain terminals when no voltage is applied to the gate terminal. It indicates that the MOSFET is normally off and requires a positive voltage at the gate terminal to create a conducting channel and allow current flow between the source and drain terminals.

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• 18.

### In a source follower, which of the electrodes receives the input signal?

• A.

Any of them (doesn’t matter)

• B.

The source

• C.

The gate

• D.

The drain

C. The gate
Explanation
In a source follower, the input signal is received by the gate electrode. The gate is connected to the input source, and it controls the flow of current between the source and the drain. The source follower is a type of field-effect transistor amplifier, where the input signal is applied to the gate and the output signal is taken from the source. The gate electrode plays a crucial role in controlling the amplification and output characteristics of the source follower circuit.

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• 19.

### Which of the following circuits produces an output signal wave that is 180° out of phase with the input signal wave?

• A.

The common source circuit

• B.

The common gate circuit

• C.

The common drain circuit

• D.

All of the above

A. The common source circuit
Explanation
The common source circuit produces an output signal wave that is 180° out of phase with the input signal wave. This is because in the common source configuration, the input signal is applied to the gate terminal and the output signal is taken from the drain terminal. The signal at the drain terminal is inverted compared to the input signal, resulting in a 180° phase shift.

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• 20.

### Which of the following circuits can produce the greatest signal gain (amplification factor)?

• A.

The common source circuit

• B.

The common gate circuit

• C.

The common drain circuit

• D.

All of the above circuits can amplify to the same extent.

A. The common source circuit
Explanation
The common source circuit can produce the greatest signal gain (amplification factor) among the given options. In this circuit configuration, the input signal is applied to the gate terminal, and the output is taken from the drain terminal. The common source configuration offers a high voltage gain and moderate current gain, making it suitable for amplification purposes. On the other hand, the common gate and common drain circuits have lower voltage gains compared to the common source circuit. Therefore, the common source circuit is the correct answer for the question.

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• Current Version
• Jun 26, 2023
Quiz Edited by
ProProfs Editorial Team
• Dec 09, 2010
Quiz Created by
BATANGMAGALING

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