Quiz On Verilog Hdl & Digital Design

20 Questions | Total Attempts: 349

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Quiz On Verilog Hdl & Digital Design

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Questions and Answers
  • 1. 
    The FPGA is abbreviated as:  
    • A. 

      First programmable Gate Array

    • B. 

      Field Programmable Gate Array

    • C. 

      Field Post Gate Array

    • D. 

      Field Program Gate Array

  • 2. 
    #40 $finish indicates
    • A. 

      End of simulation time

    • B. 

      End of simulation at 40 time units

    • C. 

      Suspend simulation at 40 time units

    • D. 

      None

  • 3. 
    The full form of VLSI is _______
    • A. 

      Very Long Single Integration

    • B. 

      Very Least Scale Integration

    • C. 

      Very Large Scale Integration

    • D. 

      Very Long Scale Integration

  • 4. 
    VHDL stands for
    • A. 

      Very High Speed Integrated Circuit Hardware Description Language

    • B. 

      Very High Description Langauge

    • C. 

      Verilog Hardware Description Language

    • D. 

      None

  • 5. 
    ASIC stands for :
    • A. 

      Application speedy integrated circuit

    • B. 

      ​​​​​​​Application specific integrated Circuit

    • C. 

      Advanced speed integrated circuit

    • D. 

      Advanced standard integrated circuit

  • 6. 
    Which model uses transistors as their basic components?
    • A. 

      Switch level

    • B. 

      Gate Level

    • C. 

      Circuit Level

    • D. 

      Layout Level

  • 7. 
    What is the default value of reg data type?
    • A. 

      0

    • B. 

      1

    • C. 

      Z

    • D. 

      X

  • 8. 
    What is the time period of clock #20 clock = ~clock
    • A. 

      10

    • B. 

      20

    • C. 

      40

    • D. 

      None

  • 9. 
    Verilog is case sensitive 
    • A. 

      Yes

    • B. 

      No

  • 10. 
    The output of the following logic =?
    • A. 

      Logic 0

    • B. 

      Logic 1

    • C. 

      X

    • D. 

      Z

  • 11. 
    The output of the following logic =? 
    • A. 

      Logic 0

    • B. 

      Logic 1

    • C. 

      X

    • D. 

      Z

  • 12. 
    Which among the following is a process of transforming RTL to gate-level netlist?
    • A. 

      Simulation

    • B. 

      Optimization

    • C. 

      Sysnthesis

    • D. 

      Verification

  • 13. 
    A 2-input XOR gate can be worked as Inverter (NOT Gate),if a =? & b =?
    • A. 

      A = a  , b =0

    • B. 

      A = a  , b =1

    • C. 

      A = b  , b= a 

    • D. 

      None

  • 14. 
     Match the following:
    • A. 

       P – 3   Q – 2  R – 1

    • B. 

       P – 3   Q–1   R – 2

    • C. 

      P – 2    Q –3    R –1

    • D. 

      None

  • 15. 
    The characteristic equation of ‘T’ Flip flop is given by
    • A. 

      Q(n+1) = T Q+T'Q'

    • B. 

      Q(n+1) = T+ Q'T'

    • C. 

      T

    • D. 

      None

  • 16. 
    The Gray code for decimal number 6 is equivalent to:
    • A. 

      1100

    • B. 

      1001

    • C. 

      0101

    • D. 

      0110

  • 17. 
    The Boolean expression (A'B+AB'+AB) is equivalent to:
    • A. 

      A+B

    • B. 

      A'+B

    • C. 

      (A+B)'

    • D. 

      A.B

  • 18. 
    The hexadecimal number ‘A0’ has the decimal value equivalent to:
    • A. 

      80

    • B. 

      256

    • C. 

      100

    • D. 

      160

  • 19. 
    (734)8=  ( )16 
    • A. 

      C1D

    • B. 

      DC1

    • C. 

      1CD

    • D. 

      1DC

  • 20. 
    The digital logic family which has minimum power dissipation is:
    • A. 

      TTL

    • B. 

      RTL

    • C. 

      DTL

    • D. 

      CMOS

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