Combinational And Sequential Circuits
(116).jpg "Combinational And Sequential Circuits - Quiz")
This is a quiz for Grade 12 to help them test their knowledge on module 4
Questions and Answers
- 1.
A ____________ gate can be used to form all other gates
Explanation
A NAND gate can be used to form all other gates because it is a universal gate. This means that any other gate, such as OR, NOT, and AND, can be constructed using only NAND gates. NAND gates are versatile and can be used to create complex logic circuits by combining them in different ways. This property makes NAND gates an essential component in digital electronics design.Rate this question:
- 2.
When we ''Set' a latch we make Q = ________?
- A.
1
- B.
0
- C.
Invalid
Correct Answer
A. 1Explanation
When we "Set" a latch, it means we are activating or enabling it. In this case, when we set the latch, the output Q will be equal to 1.Rate this question:
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- 3.
XOR and XNOR are referred to as
- A.
Sequential logic circuits
- B.
Combinational logic circuits
- C.
Basic logic gates
- D.
Complex logic gates
Correct Answer
B. Combinational logic circuitsExplanation
XOR and XNOR are referred to as combinational logic circuits because they are logic gates that produce an output based solely on the current input values. They do not have any memory or feedback, meaning that the output is determined only by the current input combination. Combinational logic circuits are used to perform specific logic operations and are essential building blocks in digital circuit design. They are different from sequential logic circuits, which have memory elements and can store information. XOR and XNOR are considered basic logic gates because they are fundamental in digital logic and can be used to build more complex circuits.Rate this question:
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- 4.
For an XOR gate having A,B as inputs and Y as output mark the incorrect entry
- A.
If A =1 and B = 1 then Y = 0
- B.
If A =0 and B = 1 then Y = 1
- C.
If A =1 and B = 0 then Y = 0
- D.
If A =0 and B = 0 then Y = 1
Correct Answer
D. If A =0 and B = 0 then Y = 1Explanation
This answer is incorrect because according to the truth table for an XOR gate, if both inputs A and B are the same (either both 0 or both 1), then the output Y should be 0. Therefore, the correct entry should be "If A = 0 and B = 0 then Y = 0".Rate this question:
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- 5.
is the logical function for
- A.
XNOR
- B.
NOR
- C.
NAND
- D.
XOR
Correct Answer
A. XNORExplanation
The XNOR function is the logical function that returns true if both inputs are either both true or both false. It is the opposite of the XOR function, which returns true if the inputs are different. The NOR function returns true if both inputs are false, while the NAND function returns true if at least one input is false. Therefore, the correct answer is XNOR.Rate this question:
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- 6.
A logic device that changes its output state in response to a HIGH or LOW level of the clock signal.
- A.
EDGE triggered latch
- B.
LEVEL triggered latch
- C.
XOR gate
- D.
NOR GATE
Correct Answer
B. LEVEL triggered latchExplanation
A LEVEL triggered latch is a logic device that changes its output state in response to a HIGH or LOW level of the clock signal. Unlike an EDGE triggered latch, which changes state only at the rising or falling edge of the clock signal, a LEVEL triggered latch responds to the continuous level of the clock signal. This means that the output state of the latch will change and remain in that state as long as the clock signal remains at the specified level.Rate this question:
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- 7.
- A ___________ latch is used to eliminate the undesirable invalid state occurs in the S-R latch :
- A.
Clocked S-R latch
- B.
D latch
- C.
Edge triggered S-R latch
- D.
Multiplexer
Correct Answer
B. D latchExplanation
A D latch is used to eliminate the undesirable invalid state that occurs in the S-R latch. Unlike the S-R latch, the D latch has only one input, the D (data) input, which determines the state of the latch. The D latch also has an enable input, which controls when the latch is allowed to change its state. This enables the D latch to eliminate the invalid state that can occur in the S-R latch when both the S and R inputs are high (1) simultaneously. By using a D latch, the system can ensure that only one input is changing at a time, preventing the occurrence of the invalid state.Rate this question:
- 8.
Latches and flip-flops are examples of sequential circuits
- A.
True
- B.
False
Correct Answer
A. TrueExplanation
Latches and flip-flops are examples of sequential circuits because they both store and transmit information in a sequential manner. Sequential circuits are designed to have memory and can remember previous inputs, allowing them to produce different outputs based on the current input as well as the past inputs. Latches and flip-flops are widely used in digital electronics for various applications, such as memory units, counters, and registers.Rate this question:
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- 9.
A D latch can have both Q and Q BAR the same
- A.
True
- B.
False
Correct Answer
B. FalseExplanation
A D latch cannot have both Q and Q BAR (complement of Q) the same because they are meant to be opposite or complementary to each other. In a D latch, Q represents the output signal and Q BAR represents the complement of the output signal. They should always have opposite logic states to ensure proper functioning of the latch. Therefore, the statement is false.Rate this question:
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- 10.
A JK-FF has no Invalid State
- A.
True
- B.
False
Correct Answer
A. TrueExplanation
A JK-FF, also known as a J-K flip flop, is a type of sequential logic circuit that has two inputs, J (set) and K (reset), and two outputs, Q (output) and Q' (complement output). In a JK-FF, the combination of inputs 0 and 0 is considered an invalid state, as it can cause unpredictable behavior. However, by using additional logic gates, it is possible to eliminate this invalid state and ensure that the JK-FF has no invalid state. Therefore, the statement "A JK-FF has no Invalid State" is true.Rate this question:
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- 11.
To set a latch mean to make its output Q low
- A.
True
- B.
False
Correct Answer
B. FalseExplanation
Setting a latch means to change the state of its output, not necessarily to make it low. A latch can be set to either a high or low state depending on the input signals. Therefore, the given statement is false.Rate this question:
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- 12.
What combination of R and S would lead to an invalid state?
- A.
R = 0 S = 0
- B.
R = 1 S = 0
- C.
R = 1 S = 1
- D.
R = 0 S = 1
Correct Answer
C. R = 1 S = 1Explanation
The combination of R = 1 and S = 1 would lead to an invalid state because it violates the rules of a specific system or context. In some systems, when both R and S are set to 1, it can result in undefined or unpredictable behavior. This could be due to a conflict in the logic or functionality of the system, causing it to be unable to determine the correct response or output. Therefore, this particular combination is considered invalid and should be avoided.Rate this question:
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- 13.
How does the NOT gate in a D flip flop help?
- A.
By making both S and R have the same value
- B.
By making both S and R have the opposite values
- C.
None of the above
Correct Answer
B. By making both S and R have the opposite valuesExplanation
The NOT gate in a D flip flop helps by making both S and R have the opposite values. This is because the D flip flop uses a set (S) and reset (R) input to control its behavior. When the NOT gate is applied to one of these inputs, it inverts the signal, causing the other input to have the opposite value. This ensures that only one input is active at a time, preventing any conflicting signals and maintaining the stability of the flip flop's output.Rate this question:
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- 14.
A latch i called BISTABLE because it has stable states.: ( More than 1 correct answer)
- A.
Q = 0
- B.
Q NOT =1
- C.
Q =1 and Q = 0
- D.
Q =HIGH and Q =LOW
Correct Answer(s)
C. Q =1 and Q = 0
D. Q =HIGH and Q =LOWExplanation
A latch is called bistable because it has stable states, meaning that it can hold and maintain two different output values. In the case of Q = 1 and Q = 0, the latch is in one stable state where Q is high and Q NOT is low. In the case of Q = HIGH and Q = LOW, the latch is in another stable state where Q is low and Q NOT is high. Both of these combinations represent the stable states of a bistable latch.Rate this question:
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- 15.
Both latches and flip-flops are circuit elements whose output depends not only on the current inputs, but also on previous inputs and outputs.
- A.
True
- B.
False
Correct Answer
A. TrueExplanation
Both latches and flip-flops are sequential logic elements that store and remember previous inputs and outputs. They have memory capabilities and can hold data until it is updated. This allows them to remember and process information based on past inputs, making their output dependent on both current and previous inputs and outputs. Therefore, the statement that both latches and flip-flops rely on current and previous inputs and outputs is true.Rate this question:
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- 16.
A negative edge in a clock signal means the voltage:
- A.
Goes from 0 to 5 volts
- B.
Goes from 5 to 0 volts
- C.
Remains at 0
- D.
Remains at 5 volts
Correct Answer
B. Goes from 5 to 0 voltsExplanation
A negative edge in a clock signal refers to the transition of voltage from a higher value (5 volts) to a lower value (0 volts). It indicates a change in state or a triggering event for certain operations or circuits.Rate this question:
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- 17.
In a clocked SR latch the outputs of the latch change when:
- A.
Clock is 0
- B.
Clock is 1
- C.
Does not depend on clock
- D.
None of the above
Correct Answer
B. Clock is 1Explanation
In a clocked SR latch, the outputs of the latch change when the clock is 1. This means that the state of the latch is only updated when the clock signal transitions from 0 to 1. When the clock is 0, the latch holds its current state and does not change. Therefore, the outputs of the latch are dependent on the clock signal and change only when the clock is 1.Rate this question:
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- 18.
This is the logic symbol of
- A.
Clocked SR latch
- B.
Edge triggered JK flip flop
- C.
JK flip flop
- D.
D flip flop
Correct Answer
B. Edge triggered JK flip flopExplanation
The given logic symbol represents an edge triggered JK flip flop. This type of flip flop is triggered by a change in the clock signal, specifically the rising or falling edge. It has two inputs, J and K, which are used to set or reset the flip flop based on the current state and the clock signal. This type of flip flop is commonly used in digital circuits to store and synchronize data.Rate this question:
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- 19.
A positive edge in a clock signal means the voltage:
- A.
Goes from 0 to 5 volts
- B.
Goes from 5 to 0 volts
- C.
Remains at 5 volts
- D.
Remains at 0 volts
Correct Answer
A. Goes from 0 to 5 voltsExplanation
A positive edge in a clock signal refers to the transition of voltage from a low state (0 volts) to a high state (5 volts). This indicates the start of a new clock cycle or the rising edge of the clock signal.Rate this question:
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- 20.
What type of logic gate can be used in a staicase switch?
- A.
AND
- B.
OR
- C.
NAND
- D.
XOR
Correct Answer
D. XORExplanation
An XOR gate, also known as an Exclusive OR gate, can be used in a staircase switch. This is because an XOR gate outputs a high signal only when the number of high inputs is odd. In a staircase switch, each step has two switches - one at the top and one at the bottom. The XOR gate can be used to control the lights of the staircase, ensuring that the lights are turned on only when an odd number of switches are activated. This allows for convenient and efficient control of the staircase lighting.Rate this question:
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Current Version
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Mar 21, 2023Quiz Edited by
ProProfs Editorial Team -
Mar 04, 2012Quiz Created by
RayanCarvalho
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