Digital Electronics Test 1

28 Questions | Total Attempts: 13220

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Digital Electronics Test 1

Questions and Answers
  • 1. 
    When 1100010 is divided by 1010, what will be the decimal reminder?
    • A. 

      2

    • B. 

      3

    • C. 

      4

    • D. 

      6

  • 2. 
    Convert (27.4)10 to its equivalent base 4 number
    • A. 

      123.1212

    • B. 

      124.1313

    • C. 

      123.2121

    • D. 

      124.1212

  • 3. 
    Convert (CAD)16 to its equivalent octal number
    • A. 

      (6355)8

    • B. 

      (6255)8

    • C. 

      (6455)8

    • D. 

      (6555)8

  • 4. 
    Add (10111)2 and (11001)2
    • A. 

      (110011)2

    • B. 

      (110001)2

    • C. 

      (110000)2

    • D. 

      (100001)2

  • 5. 
    Obtain the 2's complement of (1011 0010)2
    • A. 

      (1110 1110)2

    • B. 

      (0100 1110)2

    • C. 

      (0100 1100)2

    • D. 

      (1100 1100)2

  • 6. 
    BCD conversion of (174)10 and (2479)10 is:
    • A. 

      0001 0111 0100 and 0010 0100 0111 1011

    • B. 

      0001 0111 0111 and 0010 0100 0111 1001

    • C. 

      0001 0111 0100 and 0010 0100 0111 1001

    • D. 

      0001 0100 0100 and 0010 0100 0100 1001

  • 7. 
    2421 code is ​self complimenting
    • A. 

      True

    • B. 

      False

  • 8. 
    (FC2)16 X (DE0)16 = ?
    • A. 

      (D2A3C)16

    • B. 

      (D3A3C)16

    • C. 

      (D4A3C)16

    • D. 

      (D3A2C)16

  • 9. 
    Simplify the expression given: Y = AB + (A+B)(A'+B)
    • A. 

      Y = A

    • B. 

      Y = A'

    • C. 

      Y = B

    • D. 

      Y = B'

  • 10. 
    Minimize: Y = AB' + BC + AC
    • A. 

      A + B

    • B. 

      AB' + BC

    • C. 

      B + C

    • D. 

      BC + AC

  • 11. 
    Let f(A+B) = A' + B. Then the value of f[f(x+y,y),z] is
    • A. 

      Xy + z

    • B. 

      X'y + z

    • C. 

      Xy' + z

    • D. 

      X

  • 12. 
    Convert the expression Y=AB+AC'+BC into standard SOP form  
    • A. 

      ABC+ABC'+AB'C'+A'BC

    • B. 

      ABC+AB'C'+AB'C'+A'BC

    • C. 

      ABC+ABC'+A'B'C'+A'BC

    • D. 

      ABC+ABC'+AB'C'+A'BC'

  • 13. 
    For n=3 what is the total number of logical expressions?​ Where n is the number of variables.
    • A. 

      16

    • B. 

      64

    • C. 

      128

    • D. 

      256

  • 14. 
    In the circuit shown, the propagation delay of each NOT gate is 100 psec. Then the frequency of generated square wave is:
    • A. 

      10 GHz

    • B. 

      100 MHz

    • C. 

      1 GHz

    • D. 

      10 MHz

  • 15. 
    In TTL logic the unused input of AND gate is left open or float
    • A. 

      True

    • B. 

      False

  • 16. 
    The figure​ shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs shown in figure, the output Y is
    • A. 

      0

    • B. 

      AB

    • C. 

      1

    • D. 

      (AB)'

  • 17. 
    Exclusive NOR gate is also called as odd 1's detector
    • A. 

      True

    • B. 

      False

  • 18. 
    Minimum number of NOR gates required to implement X-NOR gate is
    • A. 

      3

    • B. 

      4

    • C. 

      5

    • D. 

      6

  • 19. 
    Minimize the following expression using K-map.Y = ∑m(0,1,5,9,13,14,15)+d(3,4,7,10,11)
    • A. 

      D+(A xnor C)

    • B. 

      A+(D xnor C)

    • C. 

      D+(A xor C)

    • D. 

      A+(D xor C)

  • 20. 
    Write the simplified expression for the output in the POS form for the following expression:Y=πM(0,2,3,7)
    • A. 

      (A+C)(B'+C')(A+B)

    • B. 

      (A'+C')(B'+C')

    • C. 

      (A+C)(B+C)

    • D. 

      (A+C)(B'+C')

  • 21. 
    The expression for Sum and Carry in full adder is given by:
    • A. 

      S=A⊕B⊕Ci Co=AB+Ci(A⊕C)

    • B. 

      S=A⊕B⊕Ci Co=AB+Ci(A⊕B)

    • C. 

      S=A⊕B Co=AB+Ci(A⊕B)

    • D. 

      S=A⊕B⊕Ci Co=A+Ci(A⊕B)

  • 22. 
    Carry look-ahead​ adder is slower than normal adder
    • A. 

      True

    • B. 

      False

  • 23. 
    A 3 line to 8 line decoder, with active low outputs, is used to implement 3 variable boolean function as shown in figure 
    • A. 

      (X+Y).(X'+Y'+Z').(Y+Z)

    • B. 

      (X'+Y').(X+Y+Z).(Y'+Z')

    • C. 

      (X'+Y'+Z).(X'+Y+Z).(X+Y'+Z).(X+Y+Z')

    • D. 

      (X'+Y'+Z').(X'+Y+Z').(X+Y+Z+).(X+Y'+Z')

  • 24. 
    A 4x1 MUX is used to implement a 3-input Boolean function as shown in the figure. The Boolean function F(A, B, C) implemented is
    • A. 

      F(A,B,C) = ∑(1,2,4,6)

    • B. 

      F(A,B,C) = ∑(1,2,6)

    • C. 

      F(A,B,C) = ∑(2,5,4,6)

    • D. 

      F(A,B,C) = ∑(1,5,6)

  • 25. 
    The figure given below shows a 4 to 1 MUX to be used to implement the sum S of a 1-bit full adder with input bit P and Q and the carry input Cin. Which of the following combinations of inputs to I0,I1,I2 and I3of the MUX will realize the sum S?
    • A. 

      I0=I1=Cin ;I2=I3=Cin'

    • B. 

      I0=I1=Cin' ;I2=I3=Cin

    • C. 

      I0=I3=Cin ;I1=I2=Cin'

    • D. 

      I0=I3=Cin' ;I1=I2=Cin'

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