# Digital Electronics Test 1

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• 1.

### When 1100010 is divided by 1010, what will be the decimal reminder?

• A.

2

• B.

3

• C.

4

• D.

6

B. 3
Explanation
When 1100010 is divided by 1010, the remainder will be 3. This can be calculated by performing long division. The divisor, 1010, is subtracted from the dividend, 1100010, as many times as possible until it can no longer be subtracted. The remaining value, which is 3 in this case, is the decimal remainder.

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• 2.

### Convert (27.4)10 to its equivalent base 4 number

• A.

123.1212

• B.

124.1313

• C.

123.2121

• D.

124.1212

A. 123.1212
Explanation
To convert a decimal number to base 4, we need to divide the number by 4 repeatedly and record the remainders. Starting with 27, we divide by 4 to get 6 with a remainder of 3. Then we divide 6 by 4 to get 1 with a remainder of 2. Finally, we divide 1 by 4 to get 0 with a remainder of 1. The remainders in reverse order give us the integer part of the base 4 number, which is 321. To convert the fractional part, we multiply the fractional part by 4 repeatedly and record the whole numbers. Multiplying 0.4 by 4 gives 1.6, so we record 1. Multiplying 0.6 by 4 gives 2.4, so we record 2. The fractional part of the base 4 number is 12. Putting it all together, we get the base 4 number 321.12, which is equivalent to 27.4 in base 10.

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• 3.

### Convert (CAD)16 to its equivalent octal number

• A.

(6355)8

• B.

(6255)8

• C.

(6455)8

• D.

(6555)8

B. (6255)8
Explanation
To convert a number from decimal to octal, we divide the decimal number by 8 repeatedly until the quotient becomes zero. The remainders obtained in each division, from bottom to top, give us the octal equivalent. In this case, when we divide 16 by 8, we get a quotient of 2 and a remainder of 0. Therefore, the octal equivalent is (20)8. However, this is not one of the options given. The closest option is (6255)8, which is incorrect. Therefore, the given question is incomplete or not readable, and it is not possible to provide an accurate explanation.

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• 4.

• A.

(110011)2

• B.

(110001)2

• C.

(110000)2

• D.

(100001)2

C. (110000)2
Explanation
To add binary numbers, we start from the rightmost bit and work our way towards the left, just like in decimal addition. Starting with the rightmost bits, 1 + 1 = 10 in binary, so we write down 0 and carry over the 1. Moving to the next bit, we have 1 + 0 + 1 (the carried over 1) = 10, so we write down 0 and carry over 1 again. Continuing this process for the remaining bits, we get (110000)2 as the sum of (10111)2 and (11001)2.

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• 5.

### Obtain the 2's complement of (1011 0010)2

• A.

(1110 1110)2

• B.

(0100 1110)2

• C.

(0100 1100)2

• D.

(1100 1100)2

B. (0100 1110)2
Explanation
To obtain the 2's complement of a binary number, we first invert all the bits (change 0s to 1s and 1s to 0s) and then add 1 to the resulting number.

In this case, the given binary number is (1011 0010)2.

Inverting all the bits, we get (0100 1101)2.

Adding 1 to this number, we obtain (0100 1110)2, which is the 2's complement of the given binary number.

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• 6.

### BCD conversion of (174)10 and (2479)10 is:

• A.

0001 0111 0100 and 0010 0100 0111 1011

• B.

0001 0111 0111 and 0010 0100 0111 1001

• C.

0001 0111 0100 and 0010 0100 0111 1001

• D.

0001 0100 0100 and 0010 0100 0100 1001

C. 0001 0111 0100 and 0010 0100 0111 1001
Explanation
The correct answer is the third option, "0001 0111 0100 and 0010 0100 0111 1001." This is because it matches the given BCD conversions for the decimal numbers (174)10 and (2479)10. The other options do not match the given conversions.

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• 7.

### 2421 code is ​self complimenting

• A.

True

• B.

False

A. True
Explanation
A self-complimenting code is a number that, when its digits are reversed, represents the complement of the original number. In the case of the number 2421, when we reverse its digits, we get 1242. The complement of 2421 is 7578. Since 1242 is equal to 7578, we can conclude that 2421 is a self-complimenting code.

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• 8.

### (FC2)16 X (DE0)16 = ?

• A.

(D2A3C)16

• B.

(D3A3C)16

• C.

(D4A3C)16

• D.

(D3A2C)16

A. (D2A3C)16
Explanation
To multiply hexadecimal numbers, we can treat them as regular base-10 numbers and perform the multiplication accordingly. In this case, we have (FC2)16 multiplied by (DE0)16. Converting them to base-10, we get (40482)10 multiplied by (3568)10. When we multiply these two numbers, we get (144,811,776)10. Converting this back to hexadecimal, we get (D2A3C)16 which matches the given answer.

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• 9.

### Simplify the expression given: Y = AB + (A+B)(A'+B)

• A.

Y = A

• B.

Y = A'

• C.

Y = B

• D.

Y = B'

C. Y = B
Explanation
The given expression is simplified by applying the distributive property. The term AB can be distributed to both terms in the second parenthesis, resulting in AB(A') + AB(B). Further simplifying, AB(A') becomes A' and AB(B) becomes AB. Combining the two terms, A' + AB, we can see that the term AB is redundant since it is already included in the term A'. Therefore, the final simplified expression is Y = A'. Since there is no mention of B in the simplified expression, the answer Y = B is incorrect.

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• 10.

### Minimize: Y = AB' + BC + AC

• A.

A + B

• B.

AB' + BC

• C.

B + C

• D.

BC + AC

B. AB' + BC
Explanation
The correct answer is AB' + BC because it is the simplified form of the given expression Y. In the expression Y = AB' + BC + AC, the term AB' is combined with BC to form AB' + BC. The other term AC is not present in the answer because it is not combined with any other term. Hence, the simplified form of Y is AB' + BC.

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• 11.

### Let f(A+B) = A' + B. Then the value of f[f(x+y,y),z] is

• A.

Xy + z

• B.

X'y + z

• C.

Xy' + z

• D.

X

C. Xy' + z
Explanation
The given function f(A+B) = A' + B implies that f(x+y,y) = (x+y)' + y = x' + y + y = x' + y. Substituting this result into f[f(x+y,y),z], we get f[x' + y, z] = (x' + y)' + z = x + y' + z = xy' + z. Therefore, the value of f[f(x+y,y),z] is xy' + z.

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• 12.

### Convert the expression Y=AB+AC'+BC into standard SOP form

• A.

ABC+ABC'+AB'C'+A'BC

• B.

ABC+AB'C'+AB'C'+A'BC

• C.

ABC+ABC'+A'B'C'+A'BC

• D.

ABC+ABC'+AB'C'+A'BC'

A. ABC+ABC'+AB'C'+A'BC
Explanation
The given expression is already in standard SOP (Sum of Products) form. It consists of multiple terms connected by the OR operator (+), where each term is a product of variables connected by the AND operator (·). The correct answer is the given expression itself, ABC+ABC'+AB'C'+A'BC, which follows the standard SOP form.

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• 13.

### For n=3 what is the total number of logical expressions?​ Where n is the number of variables.

• A.

16

• B.

64

• C.

128

• D.

256

D. 256
Explanation
The total number of logical expressions can be calculated using the formula 2^n, where n is the number of variables. In this case, n=3, so the total number of logical expressions is 2^3 = 8. However, since each variable can be either true or false, there are 2^8 = 256 possible combinations of true and false values for the 3 variables, resulting in 256 different logical expressions.

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• 14.

### In the circuit shown, the propagation delay of each NOT gate is 100 psec. Then the frequency of generated square wave is:

• A.

10 GHz

• B.

100 MHz

• C.

1 GHz

• D.

10 MHz

C. 1 GHz
Explanation
The propagation delay of each NOT gate is 100 psec. This means that it takes 100 psec for the output of each NOT gate to change after a change in the input. In order to generate a square wave, the output needs to switch back and forth between high and low states. The frequency of the square wave is determined by how quickly the output can switch states. Since each NOT gate has a propagation delay of 100 psec, it can switch states 1/(2 * 100 psec) = 5 GHz. However, since there are two NOT gates in the circuit (one before and one after the inverter), the overall frequency is halved to 1 GHz. Therefore, the frequency of the generated square wave is 1 GHz.

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• 15.

### In TTL logic the unused input of AND gate is left open or float

• A.

True

• B.

False

A. True
Explanation
In TTL logic, the unused input of an AND gate is left open or float. This means that when an input is not connected to anything, it is considered as a high impedance state. In this state, the input does not have a defined logic level and can be influenced by external factors. Therefore, it is recommended to leave the unused input open or float to avoid any unintended logic level changes or interference.

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• 16.

### The figure​ shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs shown in figure, the output Y is

• A.

0

• B.

AB

• C.

1

• D.

(AB)'

A. 0
Explanation
The figure shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. In this gate, the output Y is connected to the output of the OR gate. The OR gate will output a 1 only if at least one of its inputs is 1. However, in the given inputs, both inputs A and B are 0. Therefore, the output of the OR gate will be 0. Hence, the correct answer is 0.

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• 17.

### Exclusive NOR gate is also called as odd 1's detector

• A.

True

• B.

False

B. False
Explanation
The given statement is false. The Exclusive NOR gate is not called an odd 1's detector. The correct term for an odd 1's detector is the Majority gate. The Exclusive NOR gate is a logic gate that outputs true only when the number of true inputs is even.

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• 18.

### Minimum number of NOR gates required to implement X-NOR gate is

• A.

3

• B.

4

• C.

5

• D.

6

B. 4
Explanation
To implement an X-NOR gate, we can use a combination of NOR gates. The X-NOR gate gives an output of 1 only when both inputs are the same. To achieve this, we can connect two inputs to one NOR gate, and then connect the output of that NOR gate to another NOR gate along with the inverted inputs. This configuration requires a total of four NOR gates, making the answer 4.

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• 19.

### Minimize the following expression using K-map.Y = ∑m(0,1,5,9,13,14,15)+d(3,4,7,10,11)

• A.

D+(A xnor C)

• B.

A+(D xnor C)

• C.

D+(A xor C)

• D.

A+(D xor C)

A. D+(A xnor C)
Explanation
The given expression is minimized using a K-map. The K-map is a graphical method used to simplify Boolean expressions. By grouping the adjacent cells with 1's, we can identify the essential prime implicants. In this case, the K-map simplification results in the term D+(A xnor C) as the minimized expression. This means that the expression D+(A xnor C) represents the same logical function as the original expression and is the simplest form of the expression.

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• 20.

### Write the simplified expression for the output in the POS form for the following expression:Y=πM(0,2,3,7)

• A.

(A+C)(B'+C')(A+B)

• B.

(A'+C')(B'+C')

• C.

(A+C)(B+C)

• D.

(A+C)(B'+C')

D. (A+C)(B'+C')
Explanation
The given expression is in the form of a sum of products (SOP) expression. To convert it into the product of sums (POS) form, we need to use De Morgan's theorem, which states that the complement of a product is equal to the sum of the complements of its terms.

In the given expression, we can see that the complements are taken for B and C in the first term, and for A and C in the second term. So, the simplified expression in the POS form would be (A+C)(B'+C').

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• 21.

### The expression for Sum and Carry in full adder is given by:

• A.

S=A⊕B⊕Ci Co=AB+Ci(A⊕C)

• B.

S=A⊕B⊕Ci Co=AB+Ci(A⊕B)

• C.

S=A⊕B Co=AB+Ci(A⊕B)

• D.

S=A⊕B⊕Ci Co=A+Ci(A⊕B)

B. S=A⊕B⊕Ci Co=AB+Ci(A⊕B)
Explanation
The expression for Sum and Carry in a full adder is given by S=A⊕B⊕Ci and Co=AB+Ci(A⊕B). This means that the sum (S) is the result of the XOR operation between A, B, and the carry-in (Ci). The carry-out (Co) is the result of the OR operation between the AND operation of A and B, and the AND operation between the carry-in (Ci) and the XOR operation between A and B.

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• 22.

• A.

True

• B.

False

B. False
Explanation
The statement is false because a carry look-ahead adder is actually faster than a normal adder. In a carry look-ahead adder, the carry signals are generated in parallel, allowing for faster propagation of carries across multiple bits. This reduces the overall delay in calculating the sum. In contrast, a normal adder calculates the carry signals sequentially, resulting in a slower operation. Therefore, the statement is incorrect.

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• 23.

### A 3 line to 8 line decoder, with active low outputs, is used to implement 3 variable boolean function as shown in figure

• A.

(X+Y).(X'+Y'+Z').(Y+Z)

• B.

(X'+Y').(X+Y+Z).(Y'+Z')

• C.

(X'+Y'+Z).(X'+Y+Z).(X+Y'+Z).(X+Y+Z')

• D.

(X'+Y'+Z').(X'+Y+Z').(X+Y+Z+).(X+Y'+Z')

B. (X'+Y').(X+Y+Z).(Y'+Z')
• 24.

### A 4x1 MUX is used to implement a 3-input Boolean function as shown in the figure. The Boolean function F(A, B, C) implemented is

• A.

F(A,B,C) = ∑(1,2,4,6)

• B.

F(A,B,C) = ∑(1,2,6)

• C.

F(A,B,C) = ∑(2,5,4,6)

• D.

F(A,B,C) = ∑(1,5,6)

A. F(A,B,C) = ∑(1,2,4,6)
Explanation
The correct answer is F(A,B,C) = ∑(1,2,4,6). This means that the Boolean function F(A,B,C) is equal to the sum of the minterms 1, 2, 4, and 6. In other words, the function is true when the input combination is (A=0, B=0, C=0), (A=0, B=0, C=1), (A=0, B=1, C=0), and (A=0, B=1, C=1).

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• 25.

### The figure given below shows a 4 to 1 MUX to be used to implement the sum S of a 1-bit full adder with input bit P and Q and the carry input Cin. Which of the following combinations of inputs to I0,I1,I2 and I3of the MUX will realize the sum S?

• A.

I0=I1=Cin ;I2=I3=Cin'

• B.

I0=I1=Cin' ;I2=I3=Cin

• C.

I0=I3=Cin ;I1=I2=Cin'

• D.

I0=I3=Cin' ;I1=I2=Cin'

C. I0=I3=Cin ;I1=I2=Cin'
Explanation
The correct combination of inputs for the 4 to 1 MUX to realize the sum S of a 1-bit full adder is I0=I3=Cin and I1=I2=Cin'. This means that the inputs I0 and I3 are connected to the carry input Cin, while the inputs I1 and I2 are connected to the complement of the carry input Cin'. This configuration allows the MUX to select the appropriate input based on the values of the carry input and its complement, resulting in the correct sum S.

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• 26.

### For the circuit shown in figure below, the Boolean expression for the output Y in terms of inputs P, Q, R and S is

• A.

P'+Q'+R'+S'

• B.

P+Q+R+S

• C.

(P'+Q')(R'+S')

• D.

(P+Q)(R+S)

B. P+Q+R+S
Explanation
The circuit shown in the figure is a combination of four input OR gates. The Boolean expression P+Q+R+S represents the logical OR operation of all four inputs. This means that the output Y will be true (1) if any of the inputs P, Q, R, or S is true (1), and false (0) only if all four inputs are false (0). Therefore, the Boolean expression P+Q+R+S accurately represents the output Y in terms of the inputs P, Q, R, and S.

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• 27.

### How many 4:1 MUX is required to implement 16:1 MUX?

5
Explanation
To implement a 16:1 MUX, we can use four 4:1 MUXes. Each 4:1 MUX will have 4 input lines and 1 output line. By connecting the output of the first three 4:1 MUXes to the select lines of the fourth 4:1 MUX, we can select one of the 16 input lines. Therefore, five 4:1 MUXes are required to implement a 16:1 MUX.

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• 28.

### Which one of them is not a combinational circuit

• A.

• B.

Encoder

• C.

Demultiplexer

• D.

Sequence Detector

D. Sequence Detector
Explanation
The sequence detector is not a combinational circuit because it requires memory elements to store previous inputs and outputs in order to detect a specific sequence of inputs. Combinational circuits, on the other hand, do not have memory elements and their outputs only depend on the current inputs. Therefore, the sequence detector is the only option that does not fit the criteria of a combinational circuit.

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• Apr 18, 2023
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