# MCQ Set 1 - Digital Logic And Co

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Cr4satya
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Questions: 16 | Attempts: 129

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This MCQ will help students preparing for GATE examination.

• 1.

### Find the 16's complement of BZFA

Explanation
2FA B2FA: 1011_0010_1111_1010
15s comp: 4D05 1s comp: 0100_1101_0000_0101
16s comp: 4D06 2s comp: 0100_1101_0000_0110 = 4D06

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• 2.

### Express the following numbers in decimal: (26.24)8

Explanation
26.248 = 2 * 8 + 6 + 2/8 + 4/64 = 22.3125

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• 3.

### Convcn  decimal 8.723  lo both BCD and ASCII ecdede

Explanation
8,723
BCD: 1000_0111_0010_0011
ASCII: 0_011_1000_011_0111_011_0010_011_0001

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• 4.

• 5.
• 6.

### The first two bytes of a 2M x 16 main memory have the following hex values: Byte 0 is FE Byte 1 is 01 If these bytes hold a 16-bit two's complement integer, what is its actual decimal value if: a. memory is big endian? b. memory is little endian?

Explanation
a. FE01(16) = 1111 1110 0000 00012 = -511
b. 01FE(16) = 0000 0001 1111 11102 = 510

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• 7.

### A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. a. How many bits are needed for the opcode? b. How many bits are left for the address part of the instruction? c. What is the maximum allowable size for memory? d. What is the largest unsigned binary number that can be accommodated in one word of memory?

Explanation
a. 150 instructions implies 28 (27 will only give us 128 instructions), or 8 bits for the opcode.
b. 24 - 8 = 16.
c. 216, or 32M.
d. 24 1's, or 224 -1.

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• 8.

### Suppose that a 2M x 16 main memory is built using 256K x 8 RAM chips and memory is word-addressable. a. How many RAM chips are necessary? b. How many RAM chips are there per memory word? c. How many address bits are needed for each RAM chip? d. How many address bits are needed for all of memory?

Explanation
a. 16 (8 rows of 2 columns)
b. 2
c. 256K = 218, so 18 bits
d. 2M = 221, so 21 bits

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• 9.

### Suppose we have the instruction Load 1000. Given memory and register R1 contain the values below: Assuming R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator if R1= 200 and detemine the Value loaded into AC for a. Immediate b. Direct c. Indirect Memory d. Indexed

Explanation
In the immediate addressing mode, the value loaded into the accumulator would be the immediate value itself, which is 1000. In the direct addressing mode, the value loaded into the accumulator would be the value stored at the memory address specified by the instruction, which is 1400. In the indirect memory addressing mode, the value loaded into the accumulator would be the value stored at the memory address specified by the value stored in the memory, which is 1300. In the indexed addressing mode, the value loaded into the accumulator would be the value stored at the memory address specified by the sum of the value stored in the memory and the value stored in the register R1, which is 1000.

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• 10.

### A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization is that

• A.

It does not allow simultaneous access to the intended data and its tag

• B.

It is more expensive than other types of cache organizations

• C.

The cache hit ratio is degraded if two or more blocks used alternately map onto the same block frame in the cache

• D.

Its access time is greater than that of other cache organizations

• E.

The number of blocks required for the cache increases linearly with the size of the main memory

C. The cache hit ratio is degraded if two or more blocks used alternately map onto the same block frame in the cache
Explanation
In direct mapping, each block in the main memory is mapped to a specific block frame in the cache. If two or more blocks are used alternately and they happen to map onto the same block frame in the cache, it will result in cache conflicts. This means that when one block is accessed, the other block will be evicted from the cache, leading to cache misses and a lower cache hit ratio. This is a major disadvantage of direct mapping as it can significantly degrade the cache performance.

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• 11.

### A hypothetical microprocessor communicates with its memory and peripheral over an 8-bit data bus and a 16-bit address bus. It contains an 8-bit accumulator A and two 16-bit registers: program counter PC and index register X (see diagram below) The opcode of each instruction is one byte (8 bits) long. Assume that any internal processor time is negligible, and that the time to address memory and transfer one byte in either direction over the data bus equals unity (one memory cycle). The time taken to fetch and execute the 3-byte instruction “store A in some address indexed by X” is

• A.

3

• B.

4

• C.

5

• D.

6

• E.

7

B. 4
Explanation
3 cycle for fetch and 1 cycle for store. Then total is 3+1 = 4

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• 12.

### If a cache access requires one clock cycle and handling cache misses stalls the processor for an additional five cycles, which of the following cache hit rates comes closest to achieving an average memory access of 2 cycles?

• A.

75

• B.

80

• C.

83

• D.

86

• E.

98

B. 80
Explanation
2 = h*1 + (1-h)*6 -> h=0.8

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• 13.

• 14.

13,0,4
4,9,4
8,5,4
• 15.

### What is the average access time of a system(in ns) having three levels of memory hierarchy: a cache memory, a semiconductor main memory, and magnetic disk secondary memory. The access times of these memories are 20 ns, 200 ns, and 2 ms, respectively. The cache hit ratio is 80 per cent and the main memory hit ratio is 99 per cent. a)  If access time for upper memories does not include lower memory accesses b)  If it includes

4060
4055.6
Explanation
h1 = 0.8 : cache hit ratio,
h2 = 0.99 : main memory hit ratio
atc = access time for cache
atm = access time for main memory
ats = access time for secondary memory
Then the formula for average access time is (if access time for upper memories does not include lower memory
accesses)

Aat = h1*atc + (1-h1)[atc + h2*atm + (1-h2)*(atm + ats)]

If it includes

Aat = h1*atc + (1-h1)[h2*atm + (1-h2)*ats]

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• 16.

### If the clock frequency of a computer system is 50 Mhz, what is the period of this clock in ns?

20
Explanation
F*T = 1 -> T = 1/(50*106)sn = (1*109) /(50*106)ns = 20ns

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