MCQ Set 1 - Digital Logic And Co

Express the following numbers in decimal: (26.24)₈

The first two bytes of a 2M x 16 main memory have the following hex values: Byte 0 is FE Byte 1 is 01 If these bytes hold a 16-bit two's complement integer, what is its actual decimal value if: a. memory is big endian? b. memory is little endian?

A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. a. How many bits are needed for the opcode? b. How many bits are left for the address part of the instruction? c. What is the maximum allowable size for memory? d. What is the largest unsigned binary number that can be accommodated in one word of memory?

Suppose that a 2M x 16 main memory is built using 256K x 8 RAM chips and memory is word-addressable. a. How many RAM chips are necessary? b. How many RAM chips are there per memory word? c. How many address bits are needed for each RAM chip? d. How many address bits are needed for all of memory?

Suppose we have the instruction Load 1000. Given memory and register R1 contain the values below: Assuming R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator if R1= 200 and detemine the Value loaded into AC for a. Immediate b. Direct c. Indirect Memory d. Indexed

If the clock frequency of a computer system is 50 Mhz, what is the period of this clock in ns?

If a cache access requires one clock cycle and handling cache misses stalls the processor for an additional five cycles, which of the following cache hit rates comes closest to achieving an average memory access of 2 cycles?

• 75

• 80

• 83

• 86

• 98

A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization is that

• It does not allow simultaneous access to the intended data and its tag

• It is more expensive than other types of cache organizations

• The cache hit ratio is degraded if two or more blocks used alternately map onto the same block frame in the cache

• Its access time is greater than that of other cache organizations

• The number of blocks required for the cache increases linearly with the size of the main memory

A hypothetical microprocessor communicates with its memory and peripheral over an 8-bit data bus and a 16-bit address bus. It contains an 8-bit accumulator A and two 16-bit registers: program counter PC and index register X (see diagram below) The opcode of each instruction is one byte (8 bits) long. Assume that any internal processor time is negligible, and that the time to address memory and transfer one byte in either direction over the data bus equals unity (one memory cycle). The time taken to fetch and execute the 3-byte instruction “store A in some address indexed by X” is 

• 3

• 4

• 5

• 6

• 7

Write the microinstruction sequence to implement the two word machine level instruction OR R1, X where the address mode is indicated as “indexed based addressing”, and R6 and R7 are the index and base registers, respectively a)  On a single bus organization b)  On a double bus organization

Convcn  decimal 8.723  lo both BCD and ASCII ecdede

Express the  following function  as a sum of  mintems and as  a product of maxterm: F(A,B,C,D)=B'D+A'D+BD

The parameters of a hierarchical memory system are specified as follows: Main memory size = 8K blocks Cache memory size = 512 blocks Block size = 16 words   Determine the size of the tag field(TAG,SET/BLOCK,WORD) under the following conditions: a.  Fully associative mapping      b.  Direct mapping c.  Set associative mapping with 16 blocks/set

What is the average access time of a system(in ns) having three levels of memory hierarchy: a cache memory, a semiconductor main memory, and magnetic disk secondary memory. The access times of these memories are 20 ns, 200 ns, and 2 ms, respectively. The cache hit ratio is 80 per cent and the main memory hit ratio is 99 per cent. a)  If access time for upper memories does not include lower memory accesses b)  If it includes