# Stld Quiz-6 Cse B

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Arvind
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Quizzes Created: 3 | Total Attempts: 374
Questions: 10 | Attempts: 169  Settings  .

• 1.

### Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.

• A.

True

• B.

False

• C.

None of the above

• D.

Invalid Condition

B. False
Explanation
Master-slave J-K flip-flops are actually called edge-triggered devices, not pulse-triggered or level-triggered. This is because the input data is read only at the rising or falling edge of the clock pulse, not during the entire time the clock pulse is at a LOW level.

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• 2.

### Both JK and T flip Flop are derived from :

• A.

Basic S R latch

• B.

Basic D latch

• C.

Both 1 & 2

• D.

None of the above

A. Basic S R latch
Explanation
Both JK and T flip flops are derived from the basic S R latch. This is because the S R latch is the simplest form of a flip flop, and the JK and T flip flops are modifications of the S R latch. The JK flip flop adds a toggle functionality by incorporating an additional input, while the T flip flop simplifies the input requirements by using a single input. Therefore, the correct answer is Basic S R latch.

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• 3.

### Consider a RS flip flop with both input set to 0. If a momentary ‘1’ is applied at the input S, then the output:

• A.

Q will flip from 0 to 1

• B.

Q will flip from 0 to 1 and then back to 0

• C.

Q will flip from 1 to 0

• D.

Q will flip from 1 to 0 and then back to 1

A. Q will flip from 0 to 1
Explanation
When both inputs of the RS flip flop are set to 0, the output Q is also 0. If a momentary '1' is applied at the input S, it will set the output Q to 1, causing it to flip from 0 to 1. The other input R is still 0, so it does not affect the output. Therefore, the correct answer is that Q will flip from 0 to 1.

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• 4.

### If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be:

• A.

A) SET b) RESET (OK) c) CLEAR d) Invalid a) SET b) RESET (OK) c) CLEAR d) Invalid SET

• B.

RESET

• C.

CLEAR

• D.

INVALID

B. RESET
Explanation
When an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input, it is in the RESET state. If the R input goes to 0, it will remain in the RESET state. Therefore, the correct answer is RESET.

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• 5.

### Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

• A.

Low input voltages

• B.

Asynchronous operation

• C.

Cross coupling

• D.

Gate impedance

C. Cross coupling
Explanation
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to cross coupling. Cross coupling refers to the feedback between the inputs and outputs of the latch, which helps to maintain the latched state. This feedback ensures that even if the input voltages change, the latch will continue to hold its state until explicitly reset. This is why latches constructed with NOR and NAND gates are commonly used in memory circuits and other applications where data retention is important.

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• 6.

### The advantage of a J-K flip-flop over an S-R FF is that

• A.

It has fewer gates

• B.

It has only one output

• C.

It has no invalid states

• D.

It does not require a clock input

C. It has no invalid states
Explanation
The advantage of a J-K flip-flop over an S-R flip-flop is that it has no invalid states. This means that the J-K flip-flop can avoid the possibility of entering a forbidden or undefined state, which can cause unpredictable behavior. In contrast, an S-R flip-flop can enter an invalid state if both the S and R inputs are high, resulting in an indeterminate output. By not having any invalid states, the J-K flip-flop provides more reliable and predictable operation.

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• 7.

### Which among the following is not a mode of Flip Flop representation?

• A.

Characteristic Equations

• B.

Excitation Tables

• C.

Truth Table

• D.

Variable Entered Mapping (VEM)

D. Variable Entered Mapping (VEM)
Explanation
Variable Entered Mapping (VEM) is not a mode of Flip Flop representation. The other options, characteristic equations, excitation tables, and truth tables, are commonly used methods to represent and analyze Flip Flops. Characteristic equations express the next state of a Flip Flop in terms of its present state and input, excitation tables provide the input values required to transition between states, and truth tables show the relationship between input and output states. However, Variable Entered Mapping (VEM) is not a recognized mode of Flip Flop representation.

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• 8.

### In delay flip-flop, _______ after the propagation delay.

• A.

Input follows input

• B.

Input follows output

• C.

Output follows input

• D.

Output follows output

C. Output follows input
Explanation
In a delay flip-flop, the output changes after a certain propagation delay from the input. This means that the output follows the input, indicating that the output changes based on the input signal.

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• 9.

### What would be the characteristic equation of SR latch corresponding to the K-map schematic shown below? ( symbol ‘ denotes not gate)

• A.

S + RQn

• B.

S + R’Qn

• C.

S’ + RQn

• D.

(S + RQn’)’

B. S + R’Qn
Explanation
The characteristic equation of an SR latch is a logical expression that describes the behavior of the latch. In this case, the correct answer is "S + R'Qn". This means that the output (Q) of the latch is equal to the logical OR of the inputs S and R'Qn. The prime symbol (') represents the logical NOT operation, so R' means the logical NOT of R. The expression S + R'Qn indicates that the output Q will be set to 1 when S is 1 or when R is 0 and Qn is 1.

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• 10.

### Which is the prohibited state/ condition in S-R latch and needs to be avoided due to unpredictable nature of output?

• A.

S = R = 0

• B.

S = 0, R = 1

• C.

S = 1, R = 0

• D.

S = R = 1 Back to top