GATE - Cs - Computer Organisation & Architecture - Test 1

19 Questions | Total Attempts: 77

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GATE - Cs - Computer Organisation & Architecture - Test 1 - Quiz

Read the Instructions carefully. 1. To login, enter your Name & click on the start button. Then you can see all the questions on the screen. 2. Total duration of the examination is 60 minutes. 3. The clock will be set at the server. The countdown timer at the top right corner of screen will display the remaining time available for you to complete the examination. When the timer reaches zero, the examination will end by itself. Or you can click on submit my answers if you have completed the examination before the timer reaches zero. 4. Each examination consists of 20 questions carrying a maximum of 30 marks. Out of which 10 Questions carry 1-mark each & remaining 10 Questions carry 2-marks each. 5. All Questions are of Objective type.


Questions and Answers
  • 1. 
    Consider the following sequence of micro-operations.MBR ← PCMAR ← XPC ← YMemory ← MBRWhich one of the following is a possible operation performed by this sequence?
    • A. 

      Instruction fetch

    • B. 

      Operand fetch

    • C. 

      Conditional branch

    • D. 

      Initiation of interrupt service

  • 2. 
    Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3, …, I12 is executed in this pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is
    • A. 

      132

    • B. 

      165

    • C. 

      176

    • D. 

      328

  • 3. 
    A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is
    • A. 

      4

    • B. 

      5

    • C. 

      6

    • D. 

      7

  • 4. 
    The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have at most two source operands and one destination operand. Assume that all variables are dead after this code segment.c= a + b;d= c * a;e= c + a;x= c * c;if(x > a) {   y = a * a;}else {    d = d * d;    e = e * e;}Suppose the instruction set architecture of the processor has only two registers. The only allowed compiler optimization is code motion, which moves statements from one place to another while preserving correctness. What is the minimum number of spills to memory in the compiled code?
    • A. 

      0

    • B. 

      1

    • C. 

      2

    • D. 

      3

  • 5. 
    The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment.c = a + b;d = c * a;e = c + a;x = c * c;if (x > a) {   y = a * a;}else {    d = d * d;    e = e * e;}What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? Do not apply any optimization other than optimizing register allocation.
    • A. 

      3

    • B. 

      4

    • C. 

      5

    • D. 

      6

  • 6. 
    The amount of ROM needed to implement a 4 bit multiplier is
    • A. 

      64 bits

    • B. 

      128 bits

    • C. 

      1 Kbits

    • D. 

      2 Kbits

  • 7. 
    Register renaming is done in pipelined processors
    • A. 

      As an alternative to register allocation at compile time

    • B. 

      For efficient access to function parameters and local variables

    • C. 

      To handle certain kinds of hazards

    • D. 

      As part of address translation

  • 8. 
    A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is
    • A. 

      11

    • B. 

      14

    • C. 

      16

    • D. 

      17

  • 9. 
     A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory is
    • A. 

      160 Kbits

    • B. 

      136 Kbits

    • C. 

      40 Kbits

    • D. 

      32 Kbits

  • 10. 
    The minimum number of D flip—flops needed to design a mod-258 counter is
    • A. 

      9

    • B. 

      8

    • C. 

      512

    • D. 

      258

  • 11. 
    Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?
    • A. 

      Immediate Addressing

    • B. 

      Register Addressing

    • C. 

      Register Indirect Scaled Addressing

    • D. 

      Base Indexed Addressing

  • 12. 
    On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.      Initialize the address register     Initialize the count to 500LOOP: Load a byte from device     Store in memory at address given by address register     Increment the address register     Decrement the count     If count != 0 go to LOOP Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
    • A. 

      3.4

    • B. 

      4.4

    • C. 

      5.1

    • D. 

      6.7

  • 13. 
    Consider evaluating the following expression tree on a machine with load-store architecture in which memory can be accessed only through load and store instructions. The variables abcd and e are initially stored in memory. The binary operators used in this expression tree can be evaluated by the machine only when the operands are in registers. The instructions produce result only in a register. If no intermediate results can be stored in memory, what is the minimum number of registers needed to evaluate this expression?
    • A. 

      2

    • B. 

      9

    • C. 

      5

    • D. 

      3

  • 14. 
    Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure.What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation? 
    • A. 

      4

    • B. 

      2.5

    • C. 

      1.1

    • D. 

      3

  • 15. 
    An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following.1 Valid bit1 Modified bitAs many bits as the minimum needed to identify the memory block mapped in the cache.What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?
    • A. 

      4864 bits

    • B. 

      6144 bits

    • C. 

      6656 bits

    • D. 

      5376 bits

  • 16. 
    A main memory unit with a capacity of 4 megabytes is built using 1M×1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is
    • A. 

      100 nanoseconds

    • B. 

      100*2^10 nanoseconds

    • C. 

      100*2^20 nanoseconds

    • D. 

      3200*2^20 nanoseconds

  • 17. 
    A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?Instruction         Meaning of instructionI0 :MUL R2 ,R0 ,R1             R2 ← R0 *R1I1 :DIV R5 ,R3 ,R4             R5 ← R3 /R4I2 : ADD R2 ,R5 ,R2             R2 ← R5 + R2I3 :SUB R5 ,R2 ,R6              R5 ← R2 - R6
    • A. 

      13

    • B. 

      15

    • C. 

      17

    • D. 

      19

  • 18. 
    A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively. When there is a miss in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What is the time taken for this transfer?
    • A. 

      2 nanoseconds

    • B. 

      20 nanoseconds

    • C. 

      22 nanoseconds

    • D. 

      88 nanoseconds

  • 19. 
    A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively. When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?
    • A. 

      222 nanoseconds

    • B. 

      888 nanoseconds

    • C. 

      902 nanoseconds

    • D. 

      968 nanoseconds

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