Coa Cse D: Quiz 2

24 Questions | Total Attempts: 92

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Coa Cse D: Quiz 2 - Quiz

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Questions and Answers
  • 1. 
    In case of, Zero-address instruction method the operands are stored in _____
    • A. 

      Registers

    • B. 

      Accumulators

    • C. 

      Push down stack

    • D. 

      Cache

  • 2. 
    In assembly language programming, minimum number of operands required for an instruction is/are
    • A. 

      Zero

    • B. 

      One

    • C. 

      Two

    • D. 

      Both C and D

  • 3. 
    In which addressing mode the operand is given explicitly in the instruction?
    • A. 

      Absolute

    • B. 

      Immediate

    • C. 

      Indirect

    • D. 

      Direct

  • 4. 
    In the following indexed addressing mode instruction, MOV 5(R1),LOC, the effective address is ______
    • A. 

      EA = 5+R1

    • B. 

      EA = R1

    • C. 

      EA = [R1]

    • D. 

      EA = 5+[R1]

  • 5. 
    If a system is 64 bit machine , then the length of each word will be _______
    • A. 

      4 Byte

    • B. 

      8 Byte

    • C. 

      12 Byte

    • D. 

      16 Byte

  • 6. 
    When using the Big Endian assignment to store a number, the sign bit of the number is stored in _____
    • A. 

      The higher order byte of the word

    • B. 

      The lower order byte of the word

    • C. 

      Can’t say

    • D. 

      None of the mentioned

  • 7. 
    A _______ gate is used to detect the occurrence of an overflow.
    • A. 

      NAND

    • B. 

      XOR

    • C. 

      XNOR

    • D. 

      AND

  • 8. 
    In a normal adder circuit the delay obtained in generation of the output is _______
    • A. 

      2n + 2

    • B. 

      2n

    • C. 

      n + 2

    • D. 

      None of the mentioned

  • 9. 
    A subtractor is not usually present in a computer because
    • A. 

      It is expensive

    • B. 

      It is not possible to design it

    • C. 

      The full adder will take care of subtraction

    • D. 

      None of these

  • 10. 
    Which condition code register flags will be set to 1 when result is negative?
    • A. 

      N

    • B. 

      Z

    • C. 

      V

    • D. 

      C

  • 11. 
    The 32 bit number 5A938AF2 is held in (Byte Addressed) memory using the big-endian method starting at location 100.The number held in memory location 102 is
    • A. 

      1100 0011

    • B. 

      1000 1010

    • C. 

      1000 0011

    • D. 

      1100 0111

  • 12. 
    The words are said to be ______ in memory if they begin at a byte address that is multiple of number of bytes in a word
    • A. 

      Aligned

    • B. 

      Unaligned

    • C. 

      Byte Addressable

    • D. 

      Memory words

  • 13. 
    The 64 bit number A526FFAD4AC38BF2X is held in (Byte Addressed) memory using the big-endian method starting at location 100.The number held in memory location 105 is transferred to Register R1 . What would be the binary contents of R1 ?
    • A. 

      1100 0011

    • B. 

      1100 0010

    • C. 

      1000 0011

    • D. 

      1100 0111

  • 14. 
    The instruction, Add #45,R1 does
    • A. 

      Adds the value of 45 to the address of R1 and stores 45 in that address

    • B. 

      Adds 45 to the value of R1 and stores it in R1

    • C. 

      Finds the memory location 45 and adds that content to that of R1

    • D. 

      None of these

  • 15. 
    Consider the byte register R1 = ABH . What will be contents of R1 after the execution of AShiftL #2, R1?
    • A. 

      EA

    • B. 

      2B

    • C. 

      A3

    • D. 

      F5

  • 16. 
    Which condition code register flags will be tested by Branch > 0 instruction?
    • A. 

      Zero

    • B. 

      Overflow

    • C. 

      Zero and carry

    • D. 

      Zero and negative

  • 17. 
    Addressing mode used in instruction Add r1,r2,r3 is______
    • A. 

      Registers

    • B. 

      Index addressing mode

    • C. 

      Indirect addressing mode

    • D. 

      Offset addressing mode

  • 18. 
    Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side. 1. A[1] = B[J]; a. Indirect addressing 2. while [*A++]; b. Indexed addressing 3. int temp = *x; c. Autoincrement
    • A. 

      (1, c), (2, b), (3, a)

    • B. 

       (1, a), (2, c), (3, b)

    • C. 

      (1, b), (2, c), (3, a)

    • D. 

      (1, a), (2, b), (3, c)

  • 19. 
    The instruction ADD R1, 30FF is of _____
    • A. 

      A 3-address instruction format

    • B. 

      A 2-address instruction format

    • C. 

      A 1-address instruction format

    • D. 

      A 0-address instruction format

  • 20. 
    Displacement addressing mode will have example
    • A. 

      Add R4,R3

    • B. 

      Add R4,#3

    • C. 

      Add R4,100(R1)

    • D. 

      Add R3,(R1 + R2)

  • 21. 
    When using the Little Endian assignment to store a number, the sign bit of the number is stored in _____
    • A. 

      The higher order byte of the word

    • B. 

      The lower order byte of the word

    • C. 

      Can’t say

    • D. 

      None of the mentioned

  • 22. 
    Whenever a memory location is used, then actual memory address specified through addressing mode, is called the
    • A. 

      Effective address

    • B. 

      Registry

    • C. 

      Immediate address

    • D. 

      None of the mentioned

  • 23. 
    Let’s say that the word EFBACDFE16 is stored in a memory which is byte addressable, little endianness is followed and 1 word = 2 bytes. Which of the following gives the correct order of bytes storage of the word in memory?
    • A. 

      EF DC AB FE

    • B. 

      BA EF FE CD

    • C. 

      FE CD BA EF

    • D. 

      EF BA CD FE

  • 24. 
    Consider the byte registers R0 = ABH and R1 = ABH (H stands for Hexadecimal). What will be contents of R0 and R1 after the execution of the instruction Compare R1, R0?
    • A. 

      R0 = ABH and R1 = ABH

    • B. 

      R0 = ABH and R1 = 00H

    • C. 

      R0 = 00H and R1 = 00H

    • D. 

      R0 = 00H and R1 = ABH

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