Coa Cse D: Quiz 2
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In case of, Zero-address instruction method the operands are stored in _____
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Registers
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Accumulators
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Push down stack
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Cache
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COA CSE D: Quiz 2 assesses knowledge in computer architecture, focusing on instruction methods, assembly language, addressing modes, system architecture, and data storage. It is designed to test understanding of core concepts and their application in a 64-bit computing environment.
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- 2.
In assembly language programming, minimum number of operands required for an instruction is/are
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Zero
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One
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Two
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Both C and D
Correct Answer
A. ZeroExplanation
In assembly language programming, the minimum number of operands required for an instruction is zero. This means that there are instructions that do not require any operands to perform their operation. These instructions are typically used for simple operations or for instructions that do not require any input or output.Rate this question:
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- 3.
In which addressing mode the operand is given explicitly in the instruction?
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Absolute
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Immediate
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Indirect
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Direct
Correct Answer
A. ImmediateExplanation
Immediate addressing mode is the addressing mode in which the operand is given explicitly in the instruction. This means that the value of the operand is directly specified in the instruction itself, rather than being stored in a memory location or calculated using an expression. Immediate addressing mode is commonly used for constants or immediate values that need to be used in arithmetic or logical operations.Rate this question:
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- 4.
In the following indexed addressing mode instruction, MOV 5(R1),LOC, the effective address is ______
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EA = 5+R1
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EA = R1
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EA = [R1]
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EA = 5+[R1]
Correct Answer
A. EA = 5+[R1]Explanation
The given instruction MOV 5(R1),LOC uses indexed addressing mode. In this mode, the effective address is calculated by adding the displacement value (5) to the value stored in the register R1. Therefore, the effective address is EA = 5 + [R1].Rate this question:
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- 5.
If a system is 64 bit machine , then the length of each word will be _______
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4 Byte
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8 Byte
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12 Byte
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16 Byte
Correct Answer
A. 8 ByteExplanation
In a 64-bit machine, the length of each word is typically 8 bytes. This is because a 64-bit machine has a 64-bit processor, which means it can handle data in 64-bit chunks or words. Each word consists of 8 bytes, where each byte is 8 bits. This allows the processor to process larger amounts of data at a time, resulting in improved performance and efficiency compared to a 32-bit machine.Rate this question:
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- 6.
When using the Big Endian assignment to store a number, the sign bit of the number is stored in _____
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The higher order byte of the word
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The lower order byte of the word
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Can’t say
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None of the mentioned
Correct Answer
A. The higher order byte of the wordExplanation
In Big Endian assignment, the most significant byte of a word is stored in the higher order byte position. Since the sign bit of a number is typically located in the most significant bit of a byte, it follows that the sign bit of the number will be stored in the higher order byte of the word.Rate this question:
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- 7.
A _______ gate is used to detect the occurrence of an overflow.
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NAND
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XOR
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XNOR
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AND
Correct Answer
A. XORExplanation
An XOR gate is used to detect the occurrence of an overflow because it produces a high output only when the number of high inputs is odd. In the case of detecting an overflow, an XOR gate can be used to compare the carry-out from the most significant bit (MSB) with the carry-in to the MSB. If the two inputs are different, indicating an overflow, the XOR gate will output a high signal.Rate this question:
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- 8.
In a normal adder circuit the delay obtained in generation of the output is _______
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2n + 2
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2n
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n + 2
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None of the mentioned
Correct Answer
A. 2n + 2Explanation
In a normal adder circuit, the delay obtained in the generation of the output is 2n + 2. This means that for an n-bit adder, there will be a delay of 2n + 2 time units before the output is generated. The delay is determined by the number of stages in the adder circuit, which is equal to the number of bits in the input. Each stage introduces a delay of 1 time unit, and there are 2n stages in total. Additionally, there are 2 extra time units for the carry propagation and final output generation. Therefore, the total delay is 2n + 2.Rate this question:
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- 9.
A subtractor is not usually present in a computer because
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It is expensive
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It is not possible to design it
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The full adder will take care of subtraction
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None of these
Correct Answer
A. The full adder will take care of subtractionExplanation
A subtractor is not usually present in a computer because the full adder can perform both addition and subtraction operations. The full adder has the capability to subtract by using the concept of two's complement, which allows for efficient subtraction without the need for a separate subtractor circuit. Therefore, there is no need to include a separate subtractor in a computer system.Rate this question:
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- 10.
Which condition code register flags will be set to 1 when result is negative?
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N
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Z
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V
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C
Correct Answer
A. NExplanation
The condition code register flag N will be set to 1 when the result is negative. This flag indicates that the result of an operation is negative, meaning that the most significant bit of the result is 1.Rate this question:
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- 11.
The 32 bit number 5A938AF2 is held in (Byte Addressed) memory using the big-endian method starting at location 100.The number held in memory location 102 is
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1100 0011
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1000 1010
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1000 0011
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1100 0111
Correct Answer
A. 1000 1010Explanation
The given memory layout represents a big-endian method, where the most significant byte is stored at the lowest memory address. Since the number is 32 bits long, it is stored across four memory locations starting from location 100. The number held in memory location 102 corresponds to the second byte of the 32-bit number, which is "1000 1010" in binary. Therefore, the correct answer is "1000 1010".Rate this question:
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- 12.
The words are said to be ______ in memory if they begin at a byte address that is multiple of number of bytes in a word
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Aligned
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Unaligned
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Byte Addressable
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Memory words
Correct Answer
A. AlignedExplanation
In computer memory, words are considered to be aligned if they start at a byte address that is a multiple of the number of bytes in a word. This means that the starting address of the word is evenly divisible by the word size. Aligned memory access is important for efficient data retrieval and manipulation, as unaligned access can result in performance penalties or even errors. Therefore, the correct answer is "Aligned."Rate this question:
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- 13.
The 64 bit number A526FFAD4AC38BF2X is held in (Byte Addressed) memory using the big-endian method starting at location 100.The number held in memory location 105 is transferred to Register R1 . What would be the binary contents of R1 ?
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1100 0011
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1100 0010
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1000 0011
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1100 0111
Correct Answer
A. 1100 0011Explanation
The binary contents of R1 would be 1100 0011 because the number held in memory location 105 is transferred to R1.Rate this question:
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- 14.
The instruction, Add #45,R1 does
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Adds the value of 45 to the address of R1 and stores 45 in that address
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Adds 45 to the value of R1 and stores it in R1
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Finds the memory location 45 and adds that content to that of R1
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None of these
Correct Answer
A. Adds 45 to the value of R1 and stores it in R1Explanation
The instruction "Add #45, R1" indicates that the value of 45 should be added to the current value stored in register R1. After performing the addition, the result is stored back in register R1. This means that the value of R1 is updated by adding 45 to its previous value.Rate this question:
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- 15.
Consider the byte register R1 = ABH . What will be contents of R1 after the execution of AShiftL #2, R1?
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EA
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2B
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A3
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F5
Correct Answer
A. EAExplanation
The contents of register R1 after the execution of AShiftL #2, R1 will be EA. The AShiftL instruction performs a logical left shift operation on the value in R1 by a specified number of bits. In this case, the value in R1 (ABH) will be shifted to the left by 2 bits, resulting in EAH. Therefore, the contents of R1 after the execution will be EA.Rate this question:
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- 16.
Which condition code register flags will be tested by Branch > 0 instruction?
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Zero
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Overflow
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Zero and carry
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Zero and negative
Correct Answer
A. Zero and negativeExplanation
The Branch > 0 instruction will test the zero and negative condition code register flags. The zero flag indicates whether the result of the previous operation was zero, while the negative flag indicates whether the result was negative. By testing these flags, the instruction can determine whether the branch should be taken based on whether the previous operation resulted in a zero or negative value.Rate this question:
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- 17.
Addressing mode used in instruction Add r1,r2,r3 is______
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Registers
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Index addressing mode
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Indirect addressing mode
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Offset addressing mode
Correct Answer
A. RegistersExplanation
The given instruction "Add r1,r2,r3" uses the addressing mode of Registers. In this mode, the operands of the instruction are directly specified using registers. In this case, the values in registers r2 and r3 are added together and the result is stored in register r1. This mode is commonly used for arithmetic operations where the operands are stored in registers.Rate this question:
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- 18.
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side. 1. A[1] = B[J]; a. Indirect addressing 2. while [*A++]; b. Indexed addressing 3. int temp = *x; c. Autoincrement
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(1, c), (2, b), (3, a)
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(1, a), (2, c), (3, b)
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(1, b), (2, c), (3, a)
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(1, a), (2, b), (3, c)
Correct Answer
A. (1, b), (2, c), (3, a)Explanation
The correct answer is (1, b), (2, c), (3, a).
In statement 1, A[1] = B[J], the most natural addressing mode is indexed addressing because it involves accessing an element in an array (A) using an index (1) and another array (B) using a variable (J).
In statement 2, while [*A++], the most natural addressing mode is autoincrement because it involves accessing the value pointed to by a pointer (A) and then incrementing the pointer.
In statement 3, int temp = *x, the most natural addressing mode is indirect addressing because it involves accessing the value pointed to by a pointer (x).Rate this question:
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- 19.
The instruction ADD R1, 30FF is of _____
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A 3-address instruction format
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A 2-address instruction format
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A 1-address instruction format
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A 0-address instruction format
Correct Answer
A. A 2-address instruction formatExplanation
The instruction ADD R1, 30FF is of a 2-address instruction format. In this format, the instruction specifies both the source and destination operands within the instruction itself. In this case, the source operand is the value stored at memory address 30FF, and the destination operand is the register R1. The instruction will add the value at memory address 30FF to the value in register R1.Rate this question:
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- 20.
Displacement addressing mode will have example
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Add R4,R3
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Add R4,#3
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Add R4,100(R1)
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Add R3,(R1 + R2)
Correct Answer
A. Add R4,100(R1)Explanation
The correct answer is "Add R4,100(R1)" because this instruction uses the displacement addressing mode. In this mode, the effective address is calculated by adding the displacement value (100) to the contents of register R1. This allows the program to access memory locations that are located at a fixed distance from the base address stored in R1.Rate this question:
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- 21.
When using the Little Endian assignment to store a number, the sign bit of the number is stored in _____
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The higher order byte of the word
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The lower order byte of the word
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Can’t say
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None of the mentioned
Correct Answer
A. The lower order byte of the wordExplanation
In Little Endian assignment, the least significant byte of a word is stored first, followed by the more significant bytes. Therefore, when storing a number, the sign bit (which indicates whether the number is positive or negative) will be stored in the lower order byte of the word.Rate this question:
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- 22.
Whenever a memory location is used, then actual memory address specified through addressing mode, is called the
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Effective address
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Registry
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Immediate address
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None of the mentioned
Correct Answer
A. Effective addressExplanation
The effective address refers to the actual memory address that is specified through the addressing mode when a memory location is being used. It is the address where the data is stored or retrieved from in memory. The other options, such as registry and immediate address, do not accurately describe the concept of the actual memory address specified through addressing mode.Rate this question:
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- 23.
Let’s say that the word EFBACDFE16 is stored in a memory which is byte addressable, little endianness is followed and 1 word = 2 bytes. Which of the following gives the correct order of bytes storage of the word in memory?
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EF DC AB FE
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BA EF FE CD
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FE CD BA EF
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EF BA CD FE
Correct Answer
A. BA EF FE CDExplanation
In little endianness, the least significant byte is stored first followed by the most significant byte. In this case, the word "EFBACDFE16" is stored in memory as "BA EF FE CD".Rate this question:
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- 24.
Consider the byte registers R0 = ABH and R1 = ABH (H stands for Hexadecimal). What will be contents of R0 and R1 after the execution of the instruction Compare R1, R0?
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R0 = ABH and R1 = ABH
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R0 = ABH and R1 = 00H
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R0 = 00H and R1 = 00H
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R0 = 00H and R1 = ABH
Correct Answer
A. R0 = ABH and R1 = ABHExplanation
After the execution of the instruction Compare R1, R0, the contents of R0 and R1 will remain unchanged and will still be ABH.Rate this question:
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Sep 04, 2023Quiz Edited by
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Sep 20, 2018Quiz Created by
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