Stld Quiz-6 IT C

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Arvind
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Quizzes Created: 2 | Total Attempts: 305
Questions: 10 | Attempts: 136

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• 1.

Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.

• A.

True

• B.

False

• C.

None of the above

• D.

Invalid Condition

B. False
Explanation
Master-slave J-K flip-flops are actually called edge-triggered devices. In these flip-flops, the input data is only read at the rising or falling edge of the clock pulse, not during the entire time the clock pulse is at a LOW level. Therefore, the statement given in the question is false.

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• 2.

Both JK and T flip Flop are derived from :

• A.

Basic S R latch

• B.

Basic D latch

• C.

Both 1 & 2

• D.

None of the above

A. Basic S R latch
Explanation
Both JK and T flip flops are derived from the basic S R latch. The S R latch is a fundamental building block for sequential circuits, and the JK and T flip flops are variations of the S R latch that provide additional functionality. The JK flip flop allows for toggling between states, while the T flip flop allows for toggling when a specific condition is met. Therefore, the correct answer is the basic S R latch.

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• 3.

Consider a RS flip flop with both input set to 0. If a momentary ‘1’ is applied at the input S, then the output:

• A.

Q will flip from 0 to 1

• B.

Q will flip from 0 to 1 and then back to 0

• C.

Q will flip from 1 to 0

• D.

Q will flip from 1 to 0 and then back to 1

A. Q will flip from 0 to 1
Explanation
When both inputs of an RS flip flop are set to 0, the output remains unchanged. However, if a momentary '1' is applied at the input S, it sets the Q output to 1 while the other output Q' remains 0. Therefore, the correct answer is that Q will flip from 0 to 1.

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• 4.

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be:

• A.

A) SET b) RESET (OK) c) CLEAR d) Invalid a) SET b) RESET (OK) c) CLEAR d) Invalid SET

• B.

RESET

• C.

CLEAR

• D.

INVALID

B. RESET
Explanation
When an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input, it is in the RESET state. If the R input then goes to 0, it will remain in the RESET state. Therefore, the correct answer is RESET.

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• 5.

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

• A.

Low input voltages

• B.

Asynchronous operation

• C.

Cross coupling

• D.

Gate impedance

C. Cross coupling
Explanation
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to cross coupling. Cross coupling refers to the feedback connection between the output and input of the latch, which helps to maintain the latched state. This feedback loop ensures that once the latch is set, it remains in that state until a reset signal is received. Cross coupling is an important configuration feature that allows the latch to retain its state even when the input voltages are low or when the latch operates asynchronously.

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• 6.

The advantage of a J-K flip-flop over an S-R FF is that

• A.

It has fewer gates

• B.

It has only one output

• C.

It has no invalid states

• D.

It does not require a clock input

C. It has no invalid states
Explanation
A J-K flip-flop has no invalid states because it has two inputs, J and K, which can be used to control the state of the flip-flop. In an S-R flip-flop, if both inputs are set to 1, it can enter an invalid state where both outputs are also set to 1. This can lead to unpredictable behavior. However, in a J-K flip-flop, certain input combinations are designated as "forbidden" or "don't care" states, ensuring that it always operates in a valid and predictable manner.

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• 7.

Which among the following is not a mode of Flip Flop representation?

• A.

Characteristic Equations

• B.

Excitation Tables

• C.

Truth Table

• D.

Variable Entered Mapping (VEM)

D. Variable Entered Mapping (VEM)
Explanation
Variable Entered Mapping (VEM) is not a mode of Flip Flop representation. Flip Flops can be represented using characteristic equations, excitation tables, and truth tables. The characteristic equation represents the relationship between the current state and the next state of a Flip Flop. The excitation table shows the inputs required to transition between states. The truth table displays the outputs of the Flip Flop for all possible input combinations. However, Variable Entered Mapping (VEM) is not a recognized mode of Flip Flop representation.

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• 8.

In delay flip-flop, _______ after the propagation delay.

• A.

Input follows input

• B.

Input follows output

• C.

Output follows input

• D.

Output follows output

C. Output follows input
Explanation
In a delay flip-flop, the output follows the input after the propagation delay. This means that there is a delay between when the input signal changes and when the output signal reflects that change. The output will only change after the input has been stable for a certain amount of time, which is the propagation delay of the flip-flop.

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• 9.

What would be the characteristic equation of SR latch corresponding to the K-map schematic shown below? ( symbol ‘ denotes not gate)

• A.

S + RQn

• B.

S + R’Qn

• C.

S’ + RQn

• D.

(S + RQn’)’

B. S + R’Qn
Explanation
The characteristic equation of an SR latch determines its behavior and can be used to analyze its operation. In this case, the correct answer is "S + R'Qn." This equation represents the inputs of the SR latch, where S is the set input, R' is the reset input complemented, and Qn is the complement of the current output. This equation indicates that the next state of the latch depends on the set input and the complement of the reset input, while the output depends on the current output complemented.

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• 10.

Which is the prohibited state/ condition in S-R latch and needs to be avoided due to unpredictable nature of output?

• A.

S = R = 0

• B.

S = 0, R = 1

• C.

S = 1, R = 0

• D.

S = R = 1

D. S = R = 1
Explanation
When both S and R inputs of an S-R latch are set to 1, it creates a condition known as the "prohibited state". In this state, the output of the latch becomes unpredictable and can lead to a race condition. To avoid this unpredictable nature, it is necessary to prevent both S and R inputs from being set to 1 at the same time.

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• Sep 05, 2023
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• Nov 20, 2017
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