MIS 502 Ch 6 Quiz Drilled Down
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An interrupt handler is called by the supervisor after it looks up the interrupt code in the interrupt table.
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True
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False
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About This Quiz
MIS 502 CH 6 Quiz Drilled Down explores key concepts in operating systems and storage management. It assesses understanding of linear address spaces, device controllers, control buses, and cache operations, crucial for students in computer science and information systems.
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- 2.
An interrupt handler is called by the supervisor after it looks up the interrupt code in the interrupt table.
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True
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False
Correct Answer
A. TrueExplanation
An interrupt handler is a routine that is called by the supervisor when an interrupt occurs. The interrupt code is looked up in the interrupt table to determine which handler should be called. Therefore, the statement "An interrupt handler is called by the supervisor after it looks up the interrupt code in the interrupt table" is true.Rate this question:
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- 3.
In most computers, a(n) I/O port is a memory address, or a set of contiguous memory addresses, that can be read or written by the CPU and a single peripheral device.
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True
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False
Correct Answer
A. TrueExplanation
In most computers, an I/O port is a memory address or a set of contiguous memory addresses that can be accessed by both the CPU and a single peripheral device. This allows the CPU to read from or write to the peripheral device using these memory addresses. Therefore, the statement "True" is the correct answer as it accurately describes the relationship between the CPU, I/O ports, and peripheral devices in most computers.Rate this question:
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- 4.
The ____ is a register that always contains the address of the topmost stack element.
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Interrupt register
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Stack pointer
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Machine state
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Instruction register
Correct Answer
A. Stack pointerExplanation
The stack pointer is a register that always contains the address of the topmost stack element. It keeps track of the current position of the stack and is used to push and pop elements onto and from the stack. The stack pointer is crucial in managing the stack data structure and ensuring that elements are properly organized and accessible.Rate this question:
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- 5.
During a push operation, one or more register values are copied to the top of the stack.
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True
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False
Correct Answer
A. TrueExplanation
During a push operation, register values are indeed copied to the top of the stack. This is a common operation in computer programming, where values stored in registers need to be temporarily saved onto the stack for later use. The push operation involves decrementing the stack pointer and then copying the register values onto the stack at the new top position. This allows the program to free up the registers for other operations while still retaining the values for future use.Rate this question:
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- 6.
SCSI is a proprietary standard and manufacturers of SCSI devices must pay a license fee.
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True
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False
Correct Answer
A. FalseExplanation
SCSI is not a proprietary standard, but rather an industry standard that is not owned by any specific company. Manufacturers of SCSI devices do not have to pay a license fee to use the SCSI standard. Therefore, the statement is false.Rate this question:
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- 7.
To which bus(es) is a SCSI controller attached?
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SCSI bus
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System bus
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Both a and b
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Neither a nor b
Correct Answer
A. Both a and bExplanation
A SCSI controller can be attached to both the SCSI bus and the system bus. The SCSI bus is specifically designed for connecting SCSI devices, including SCSI controllers, while the system bus is the main communication pathway between the CPU and other components of the computer system. Therefore, a SCSI controller can be connected to both buses simultaneously, allowing for efficient data transfer and communication between the SCSI devices and the rest of the system.Rate this question:
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- 8.
The Intel Itanium2 processor has separate L1 caches for data and instructions.
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True
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False
Correct Answer
A. TrueExplanation
The Intel Itanium2 processor indeed has separate L1 caches for data and instructions. This design allows for faster and more efficient processing by enabling simultaneous access to both data and instructions. By separating the caches, the processor can fetch and store data and instructions independently, reducing the chances of cache conflicts and improving overall performance.Rate this question:
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- 9.
If two peripheral devices attempt to send a message at the same time, the messages collide and produce electrical noise.
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True
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False
Correct Answer
A. TrueExplanation
When two peripheral devices attempt to send a message at the same time, there is a possibility of their messages colliding. This collision results in electrical noise, which can disrupt the communication between the devices. Therefore, the statement "If two peripheral devices attempt to send a message at the same time, the messages collide and produce electrical noise" is true.Rate this question:
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- 10.
Which bus carries interrupts, read commands, status codes, and acknowledgements?
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System bus
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Control bus
Correct Answer
A. Control busExplanation
The control bus carries interrupts, read commands, status codes, and acknowledgements. This bus is responsible for controlling the flow of information and coordinating the operations of different components within a computer system. It allows the CPU to communicate with other devices and peripherals by sending control signals and commands. The control bus plays a crucial role in managing the overall operation and synchronization of the system.Rate this question:
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- 11.
Where does the translation from logical access to physical accesses normally take place?
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Device controller
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I/O or storage device
Correct Answer
A. Device controllerExplanation
The translation from logical access to physical accesses normally takes place in the device controller. The device controller is responsible for managing the communication between the computer system and the I/O or storage devices. It translates the logical access requests made by the computer system into physical accesses that the devices can understand and execute. This allows for efficient and effective data transfer between the computer system and the devices.Rate this question:
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- 12.
Which of the following devices does the CPU treat as a linear address space?
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Tape drive
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Disk drive
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Video display
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All of the above
Correct Answer
A. All of the aboveExplanation
The CPU treats all of the mentioned devices (tape drive, disk drive, and video display) as a linear address space. This means that the CPU views the memory addresses of these devices as a continuous sequence of locations, allowing it to access data and instructions stored in these devices using the same addressing scheme as it does for main memory. This allows for efficient and consistent communication between the CPU and these devices.Rate this question:
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- 13.
During a(n) ____ operation, one or more register values are copied to the top of the stack.
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Pop
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Push
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Swap
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Shift
Correct Answer
A. PushExplanation
During a push operation, one or more register values are copied to the top of the stack. This means that the register values are pushed onto the stack, effectively adding them to the top of the stack. This is a common operation in stack-based architectures, where values are stored and retrieved from the stack in a last-in, first-out (LIFO) manner. The push operation allows for efficient storage and retrieval of data in a stack structure.Rate this question:
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- 14.
____ enable the CPU and bus to interact with a keyboard in exactly the same way they interact with a disk drive or video display.
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Caches
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I/O ports
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Buffers
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DMA controllers
Correct Answer
A. I/O portsExplanation
I/O ports enable the CPU and bus to interact with a keyboard in the same way they interact with a disk drive or video display. I/O ports are hardware components that provide a means for the CPU to send and receive data to and from external devices. They allow the CPU to communicate with peripherals, such as keyboards, by providing specific addresses and protocols for data transfer. This allows the CPU and bus to treat the keyboard as a standard input/output device, just like a disk drive or video display.Rate this question:
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- 15.
Using ____ alters the balance of processor resources and communication or storage resources in a computer system.
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Compression ratio
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Data compression
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Lossy compression
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Lossless compression
Correct Answer
A. Data compressionExplanation
Data compression is the process of reducing the size of data files, which in turn affects the balance of processor resources and communication or storage resources in a computer system. By compressing data, the overall amount of data that needs to be processed or stored is reduced, allowing for more efficient use of resources. This can be particularly beneficial in situations where there are limitations on processing power or storage capacity, as data compression helps optimize the utilization of these resources.Rate this question:
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- 16.
The ____ is a register that always contains the address of the topmost stack element.
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Interrupt register
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Stack pointer
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Machine state
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Instruction register
Correct Answer
A. Stack pointerExplanation
The stack pointer is a register that always contains the address of the topmost stack element. It is used to keep track of the current position in the stack, allowing for efficient push and pop operations. By storing the address of the topmost element, the stack pointer enables easy access to the most recently added data on the stack.Rate this question:
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- 17.
The CPU is always capable of being a(n) ____, thus controlling access to the bus by all other devices in the computer system.
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Bus arbitration unit
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Bus slave
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Bus master
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Peripheral processing unit
Correct Answer
A. Bus masterExplanation
The CPU is always capable of being a bus master, thus controlling access to the bus by all other devices in the computer system. As a bus master, the CPU has the authority to initiate and manage data transfers between different devices connected to the bus. It can request data from or send data to other devices, ensuring efficient communication and coordination within the computer system.Rate this question:
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- 18.
The machine state is a register that always contains a pointer to the top of the stack.
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True
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False
Correct Answer
A. FalseExplanation
The machine state is not always a register that contains a pointer to the top of the stack. The machine state refers to the complete snapshot of the system at any given point in time, including the values of all registers, memory locations, and other relevant information. While a stack pointer register may be part of the machine state, it is not always the case. Therefore, the statement is false.Rate this question:
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- 19.
Which of the following is a potential source of an interrupt?
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Opening a non-existent file
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Opening a file that exists
Correct Answer
A. Opening a non-existent fileExplanation
When a program attempts to open a non-existent file, it can trigger an interrupt. This interrupt occurs because the operating system needs to handle the error and notify the program that the file does not exist. The interrupt allows the operating system to take control and perform necessary actions, such as displaying an error message or terminating the program gracefully. In contrast, opening a file that exists does not typically result in an interrupt since it is a normal operation that the operating system can handle without any issues.Rate this question:
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- 20.
During interrupt processing, register values of a suspended process are stored ____.
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On the stack
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In a cache
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In a buffer
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In a linear address space
Correct Answer
A. On the stackExplanation
During interrupt processing, the register values of a suspended process are stored on the stack. The stack is a data structure that allows for efficient last-in, first-out (LIFO) operations. When an interrupt occurs, the processor saves the current state of the process by pushing the register values onto the stack. This allows the processor to resume execution of the interrupted process later on by popping the saved register values from the stack and restoring them back into the appropriate registers. Storing the register values on the stack ensures that they are easily accessible and can be efficiently restored when needed.Rate this question:
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- 21.
____ enable the CPU and bus to interact with a keyboard in exactly the same way they interact with a disk drive or video display.
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Caches
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I/O ports
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Buffers
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DMA controllers
Correct Answer
A. I/O portsExplanation
I/O ports enable the CPU and bus to interact with a keyboard in exactly the same way they interact with a disk drive or video display. I/O ports are hardware components that provide a means for the CPU to communicate with external devices, such as keyboards, by sending and receiving data. They allow the CPU to send commands and receive input from the keyboard, just as it would with other devices like a disk drive or video display.Rate this question:
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- 22.
A cache controller is a hardware device that initiates a cache swap when it detects a(n) ____.
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Cache miss
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Cache hit
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Interrupt
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Stack overflow
Correct Answer
A. Cache missExplanation
A cache controller is responsible for managing data in a cache memory. When it detects a cache miss, it means that the requested data is not present in the cache memory. In this case, the cache controller initiates a cache swap, which involves fetching the required data from the main memory and storing it in the cache for faster access in the future.Rate this question:
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- 23.
Secondary storage devices are not generally attached directly to the system bus. Instead, they are attached to a(n) ____ which is, in turn, attached to the system bus.
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Bus port
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Access arm
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Drive array
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Device controller
Correct Answer
A. Device controllerExplanation
Secondary storage devices, such as hard drives or optical drives, are not directly connected to the system bus. Instead, they are connected to a device controller, which acts as an intermediary between the storage device and the system bus. The device controller manages the communication and data transfer between the storage device and the system bus, allowing the system to access and retrieve data from the secondary storage.Rate this question:
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- 24.
How many memory cache levels are employed by the Intel Itanium2 processor?
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0
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1
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2
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3
Correct Answer
A. 3Explanation
The Intel Itanium2 processor employs three memory cache levels. This means that it has three levels of cache memory, each with different sizes and speeds. These cache levels are used to store frequently accessed data and instructions, allowing for faster processing and reducing the need to access data from the main memory. Having multiple cache levels helps to improve the overall performance and efficiency of the processor.Rate this question:
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- 25.
The operating system normally views any storage device as a(n) ____, thus ignoring the device's physical storage organization.
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Device controller
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Peripheral processing unit
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Linear address space
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Multiple master bus
Correct Answer
A. Linear address spaceExplanation
The operating system normally views any storage device as a linear address space. This means that the operating system treats the storage device as a continuous sequence of memory addresses, disregarding the physical organization of the device's storage. This allows the operating system to access and manage the storage device in a uniform and efficient manner, regardless of the underlying physical structure of the device.Rate this question:
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- 26.
Which of the following statements about caches is not correct?
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During a read operation, a cache acts as a buffer.
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Data first is stored in the cache and then transferred to the storage device.
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Most of the performance benefits of a cache occur during read operations.
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Write caching can result in more significant performance improvement when one write access must be confirmed before another can begin.
Correct Answer
A. During a read operation, a cache acts as a buffer.Explanation
During a read operation, a cache does not act as a buffer. The purpose of a cache is to store frequently accessed data and provide faster access to it. In a read operation, the cache is checked first to see if the requested data is already stored. If it is, the data is retrieved from the cache and there is no need for buffering. If the data is not in the cache, it is retrieved from the storage device and then stored in the cache for future access. Therefore, the statement that a cache acts as a buffer during a read operation is incorrect.Rate this question:
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- 27.
Storage and I/O devices are normally connected to the system bus through a(n) channel.
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True
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False
Correct Answer
A. FalseExplanation
Storage and I/O devices are not normally connected to the system bus through a channel. Instead, they are typically connected through a separate I/O bus or interface. The system bus is primarily responsible for connecting the CPU and main memory, while the I/O bus handles communication between the CPU and peripheral devices. Therefore, the statement "Storage and I/O devices are normally connected to the system bus through a channel" is false.Rate this question:
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Current Version
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Mar 20, 2023Quiz Edited by
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Oct 10, 2010Quiz Created by
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