MIS 502 Ch 6 Quiz Drilled Down

27 Questions | Total Attempts: 61

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MIS 502 Ch 6 Quiz Drilled Down

MIS 502 CH 6 Quiz Drilled Down


Questions and Answers
  • 1. 
    The operating system normally views any storage device as a(n) ____, thus ignoring the device's physical storage organization.
    • A. 

      Device controller

    • B. 

      Peripheral processing unit

    • C. 

      Linear address space

    • D. 

      Multiple master bus

  • 2. 
    Where does the translation from logical access to physical accesses normally take place?
    • A. 

      Device controller

    • B. 

      I/O or storage device

  • 3. 
    Which bus carries interrupts, read commands, status codes, and acknowledgements?
    • A. 

      System bus

    • B. 

      Control bus

  • 4. 
    Which of the following devices does the CPU treat as a linear address space?
    • A. 

      Tape drive

    • B. 

      Disk drive

    • C. 

      Video display

    • D. 

      All of the above

  • 5. 
    Which of the following statements about caches is not correct?
    • A. 

      During a read operation, a cache acts as a buffer.

    • B. 

      Data first is stored in the cache and then transferred to the storage device.

    • C. 

      Most of the performance benefits of a cache occur during read operations.

    • D. 

      Write caching can result in more significant performance improvement when one write access must be confirmed before another can begin.

  • 6. 
    Which of the following is a potential source of an interrupt?
    • A. 

      Opening a non-existent file

    • B. 

      Opening a file that exists

  • 7. 
    A cache controller is a hardware device that initiates a cache swap when it detects a(n) ____.
    • A. 

      Cache miss

    • B. 

      Cache hit

    • C. 

      Interrupt

    • D. 

      Stack overflow

  • 8. 
    The CPU is always capable of being a(n) ____, thus controlling access to the bus by all other devices in the computer system.
    • A. 

      Bus arbitration unit

    • B. 

      Bus slave

    • C. 

      Bus master

    • D. 

      Peripheral processing unit

  • 9. 
    SCSI is a proprietary standard and manufacturers of SCSI devices must pay a license fee.
    • A. 

      True

    • B. 

      False

  • 10. 
    During interrupt processing, register values of a suspended process are stored ____.
    • A. 

      On the stack

    • B. 

      In a cache

    • C. 

      In a buffer

    • D. 

      In a linear address space

  • 11. 
    How many memory cache levels are employed by the Intel Itanium2 processor?
    • A. 

      0

    • B. 

      1

    • C. 

      2

    • D. 

      3

  • 12. 
    ____ enable the CPU and bus to interact with a keyboard in exactly the same way they interact with a disk drive or video display.
    • A. 

      Caches

    • B. 

      I/O ports

    • C. 

      Buffers

    • D. 

      DMA controllers

  • 13. 
    An interrupt handler is called by the supervisor after it looks up the interrupt code in the interrupt table.
    • A. 

      True

    • B. 

      False

  • 14. 
    Secondary storage devices are not generally attached directly to the system bus. Instead, they are attached to a(n) ____ which is, in turn, attached to the system bus.
    • A. 

      Bus port

    • B. 

      Access arm

    • C. 

      Drive array

    • D. 

      Device controller

  • 15. 
    The machine state is a register that always contains a pointer to the top of the stack.
    • A. 

      True

    • B. 

      False

  • 16. 
    ____ enable the CPU and bus to interact with a keyboard in exactly the same way they interact with a disk drive or video display.
    • A. 

      Caches

    • B. 

      I/O ports

    • C. 

      Buffers

    • D. 

      DMA controllers

  • 17. 
    If two peripheral devices attempt to send a message at the same time, the messages collide and produce electrical noise.
    • A. 

      True

    • B. 

      False

  • 18. 
    To which bus(es) is a SCSI controller attached?
    • A. 

      SCSI bus

    • B. 

      System bus

    • C. 

      Both a and b

    • D. 

      Neither a nor b

  • 19. 
    The ____ is a register that always contains the address of the topmost stack element.
    • A. 

      Interrupt register

    • B. 

      Stack pointer

    • C. 

      Machine state

    • D. 

      Instruction register

  • 20. 
    During a push operation, one or more register values are copied to the top of the stack.
    • A. 

      True

    • B. 

      False

  • 21. 
    Using ____ alters the balance of processor resources and communication or storage resources in a computer system.
    • A. 

      Compression ratio

    • B. 

      Data compression

    • C. 

      Lossy compression

    • D. 

      Lossless compression

  • 22. 
    During a(n) ____ operation, one or more register values are copied to the top of the stack.
    • A. 

      Pop

    • B. 

      Push

    • C. 

      Swap

    • D. 

      Shift

  • 23. 
    An interrupt handler is called by the supervisor after it looks up the interrupt code in the interrupt table.
    • A. 

      True

    • B. 

      False

  • 24. 
    In most computers, a(n) I/O port is a memory address, or a set of contiguous memory addresses, that can be read or written by the CPU and a single peripheral device.
    • A. 

      True

    • B. 

      False

  • 25. 
    The Intel Itanium2 processor has separate L1 caches for data and instructions.
    • A. 

      True

    • B. 

      False

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