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A+ Study Guide: CMOS

Memory (Cont...)
  • Level 2 Cacheable DRAM Size / Cache Over 64 MB of DRAM
    This controls how much of the system memory is “covered” by the level 2 cache.

  • DRAM Parity Checking
    When enabled, turns on parity checking for the system RAM. This must be enabled while using parity checking (or ECC), and disabled otherwise. The default is normally “Disabled” as most modern systems don't use parity memory.

  • DRAM Parity/ECC Mode
    On a system that supports both parity and ECC error detection / correction modes; this option, selects which mode is activated. ECC stands for “error correcting code” or “error correction code” and is a more advanced error detection and correction protocol than straight parity. It is ignored or disabled if “DRAM Parity Checking” is disabled.

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