SDRAM (Synchronous DRAM) was introduced in 1996. SDRAM was developed to match the ever-increasing processing speeds of the Pentium systems.
Synchronous DRAM, is synchronized to the speed of the systems (e.g. PC66 SDRAM runs at 66MHz, PCIOO runs at 100M HZ, PC133 runs at 133MHz and so on) hence the name "synchronous". Synchronizing the speed of the systems prevents the address bus from having to wait for the memory because of different clock speeds.
A SDRAM's timing is synchronized to the system clock. By running in sync to an external clock signal, SDRAM can run at the same speed as the CPU/memory bus, there by eliminating the CPU wait states. The chip is divided into two cell blocks, and data is split between the two. While a bit in one block is accessed, a bit in the other is buffered for access. This allows SDRAM to burst subsequent, contiguous characters at a much faster rate than the first character.
SDRAM are DIMMs and have 168-pins running at 3.3 volts.
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